Low power 32-bit bus with inversion encoding

1. Low power 32-bit bus with inversion encoding Wei Jiang ELEC 6270

2. Power Consumption by Bus • High capacitance lines • High switching activities • Reduce power dissipation by reducing the number of transitions

3. Bus Invert Encoding Transmitter Receiver 32 Conventional Bus Transmitter ENCODER DECODER Receiver 32 INV Bus with Inversion Encoding

4. Bus Invert Encoding • To minimize transitions in bus with large capacitance • Additional Line: INV • Encoding: • Di, if INV=0 • Di XOR 1, if INV=1 • Decoding: • Di XOR INV • Proposed by M. R. Stan

5. Design of Encoder

6. Majority voter • Majority voter circuit decides according to Hamming distance whether to invert or not the next value • Digital voter: accurate • Analog voter: simple Stan, TVLSI 1995

7. Counter & Comparator

8. Falling Edge Detector/Indicator

9. Design of Decoder

10. Simulation – Best Scenario

11. Simulation – Worst Scenario

12. Signal Transitions Total Power Dissipation Power Dissipation of Transmitter Power Dissipation of Receiver Signals forms

13. Simulation – Average

14. Conclusion • Average power by transmitter/receiver (CL=0) • For conventional bus: 0.8415mW • For inverted bus: 2.20745 mW • Encoder/Decoder overhead: 1.36595 mW • Increase the power dissipation of low capacitance bus • Reduce dynamical power dissipation by roughly 10% if bus load capacitance per bit is 1pf; 25% for 2pf of load capacitance; and more for even higher capacitance • The actual power reduction depends on both the bus load capacitance and the number of transitions: • More than 17/close to 32: bus inversion may reducing power • Less than 17: bus inversion may increase power

15. Thank You • Simulation • TSMC 0.35um Process • Synopsys HSPICE • References • M. R. Stan and W. P. Burleson, “Bus-invert coding for low-power I/O,” IEEE Trans. On VLSI Systems, Vol.3, No.1, pp.49-58, 1995 • T. Lindkvist et al, “Deep Sub-Micron Bus Invert Coding,” NORSIG 2004, p.133-136, June 2004