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Ultimate MIMO 

Ultimate MIMO . Ultimate Chip Floor Plan. Selectable analog outputs ~ 300 µm for Pads + Electronics. Shift Row Reg. Pixel sequencer + Buffer tree. Pixel Array. Column-level Discriminators. Zero suppression. ~2mm. JTAG. Memory 1. PLL. Seq. Ctrl. Memory 2. Bias-DAC. Pad Ring.

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Ultimate MIMO 

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  1. Ultimate MIMO

  2. Ultimate Chip Floor Plan Selectable analog outputs ~ 300 µm for Pads + Electronics Shift Row Reg Pixel sequencer + Buffer tree Pixel Array Column-level Discriminators Zero suppression ~2mm JTAG Memory 1 PLL Seq. Ctrl Memory 2 Bias-DAC Pad Ring Ultimate-MimoStar christine.hu@ires.in2p3.fr

  3. Functional descriptions • Pixel Array: • Pitch = f (power consumption, radiation hardness), ref. presentation 06/06 • Integration time= f (Nrow) • Different pitches for the 2 layers? • Rectangular pixels? • Matrix steering logic (width ~300 µm) • Placed on the left hand side of the matrix • Rolling shutter binary readout over 5 MHz • Require ~200 ns /row (line of 2 cm long to drive ) • Integration time = 200 ns x Nrow < = 200 µs • Zero suppression: based on SUZE01 architecture, Ref Guy's talk • Time for data reduction treatment = 1 row pixels readout time • Bias reference DAC + JTAG controller • An common reference clock 10 MHz per ladder • Internal CKgenerated viaPLL on chip • Testabilities: like M22, Ref Gilles's talk Ultimate-MimoStar christine.hu@ires.in2p3.fr

  4. Star Ultimate Chip • Zero suppression: physics condition : 2,4 x 105 hits/s/cm2 • Readout time 200 µs  ~ 200 hits/frame/sensor with safety factor of 2 (?), ~ 500 hits/frame/sensor • SUZE design: • Maximum output speed: ~100 Mbits/s • 2 memories of (200 x 3) x 32 bits • With new condition & with ~ 10-4  ~ 100 noisy pixels • Zero suppression  based on SUZE's group & row hits finders design • Points have to be changed: • Increase maximum output speed: up to 256 Mbits/s • Increase dimension of memory: 3 times larger • Memory: anti latch up? Ultimate-MimoStar christine.hu@ires.in2p3.fr

  5. Seq. Freq. Data out Freq. PLL 10 MHz Star Ultimate Chip • Clock distribution • Use PLL • Data transmission • Data format: • Study embedded clock in data stream Ultimate-MimoStar christine.hu@ires.in2p3.fr

  6. LBNL Mechanical Requirements • 3 or 4 fiducial marks/chip for optical survey • All bonding pads located along 1 side of chip • Except analog test pads • Two bonding pads per I/O (if possible) of the chip to facilitate probe testing Ultimate-MimoStar christine.hu@ires.in2p3.fr

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