Differential 2r crosspoint rram for memory system in mobile electronics with zero standby current
This presentation is the property of its rightful owner.
Sponsored Links
1 / 16

Pi-Feng Chiu, Pengpeng Lu, Zeying Xin EECS, UC Berkeley 05/06/2013 PowerPoint PPT Presentation


  • 296 Views
  • Uploaded on
  • Presentation posted in: General

Differential 2R Crosspoint RRAM for Memory system in Mobile Electronics with Zero Standby Current. Pi-Feng Chiu, Pengpeng Lu, Zeying Xin EECS, UC Berkeley 05/06/2013. Outline. Introduction Memory Hierarchy RRAM switching mechanism Issues of Crosspoint Array Proposed Differential 2R cell

Download Presentation

Pi-Feng Chiu, Pengpeng Lu, Zeying Xin EECS, UC Berkeley 05/06/2013

An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -

Presentation Transcript


Differential 2r crosspoint rram for memory system in mobile electronics with zero standby current

Differential 2R Crosspoint RRAM for Memory system in Mobile Electronics with Zero Standby Current

Pi-Feng Chiu, Pengpeng Lu, Zeying XinEECS, UC Berkeley

05/06/2013


Outline

Outline

  • Introduction

    • Memory Hierarchy

    • RRAM switching mechanism

  • Issues of Crosspoint Array

  • Proposed Differential 2R cell

    • Cell Characteristics

    • Differential 2R cell and array design

  • Circuit Implementation

    • Divided WL and Sense-before

  • Simulation Results

  • Comparison

  • Conclusion


Memory hierarchy

Memory Hierarchy

CPU Register

Leakage issue

Perfect Memory:

Nonvolatile

High speed

Small Area

Low power

High Endurance

CacheL1L2

Main Memory(DRAM)

High speed

High memory density

Permanent StorageHard Disk Drive, Solid State Drive

Slow


Rram switching mechanism

RRAM switching mechanism

  • RRAM: Resistive Random Access Memory

  • Sandwiched cell structure

  • SET: Switching to Low Resistance State (LRS)

  • RESET: Switching to High Resistance State (HRS)


Crosspoint issues

Crosspoint Issues

1T1R Crosspoint structure

Leakage issues:

Write – write energy efficiency

Read –read margin

Write Disturbance

n: BL number, m: WL number

(a)

(b)

(c)


Cell characteristics

Cell Characteristics

  • Tradeoffs

    • RLow vs. write energy

    • Write time vs. Write voltage

    • Write energy vs. Write voltage

    • Read margin vs. Rlow

    • Sensitivity to Write time


Differential 2r cell

Differential 2R cell

1 cell

BL0

BL1

BL2

WLa[1]

In read operation,

WLa=Vread, WLb=0Voltage-sensing VBL

+

Ra

-

+

VBL=Vread*Rb/(Ra+Rb)

Rb

-

WLb[1]

WLa[0]

Assumption:VSET=VRESET=Vwrite

WLb[0]


Divided wl

Divided WL

  • To constrain overall write current to 100~200uA, WL length need to be set to 4-cell wide

  • Divided WL: decouple local WLs and connect to global WL by switches.

  • Tradeoff between leakage current and area penalty

GWLb

BEOL process enables stack ability

GWLa

LWLa

Ra

Rb

LWLb

BL

SWa

SWb


Sense before write

Sense-before-Write

  • Resistance value drops if a SET pulse repeatedly access to the cell.

  • Solution:

Lowest resistance value

Targeted resistance value

I(cell)

DIN

If DIN=DOUT ?

Write?

Read

Yes

Pass

DOUT

No

Write


Block diagram

Block diagram


Pi feng chiu pengpeng lu zeying xin eecs uc berkeley 05 06 2013

Write-0to cell01

Write-1to cell11

WLa[0]

0

WLb[0]

WLa[1]

~Vwrite/2

WLb[1]

Vref

BL[1]

~Vwrite

DOUT

R1

R0

SET

I(cell01b)

RESET

I(cell01a)

Write operation

Read operation


Features

Features


Comparison

Comparison

*: assume metal width and space are 50nm, area = (0.05*4)2

Fit for L2/L3 cache in mobile electronics to save battery life


Conclusion

Conclusion

  • Differential 2R crosspoint RRAM design

    • 64KB RRAM circuit

    • Divided WL and Sense-before-Write approach

    • 28/32nm PTM, RRAM cell model, Eldo simulator

  • Crosspoint RRAM  Cache?

    • Area: yes

    • Power: depending on application

    • Endurance

  • Future Work:

    • Cell characterization

    • Leakage reduction, Cell distribution

?


Thanks

Thanks!


Reference

Reference

  • ITRS Roadmap (http://www.itri.net)

  • Yan Li, et al., “128Gb 3b/cell NAND Flash Memory in 19nm Technology with 18MB/s Write Rate and 400Mb/s Toggle Mode,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2012, pp. 436-437.

  • T. Takashima, et al., “A 100MHz Ladder FeRAM Design With Capacitance-Coupled-Bitline (CCB) Cell,” IEEE Journal of Solid-State Circuits, Vol. 46, No. 3, March 2011.

  • T. Shigibayashi, et al., “A 16-Mb Toggle MRAM With Burst Modes,” IEEE Journal of Solid-State Circuits, Vol. 42, No. 11, Nov. 2007.

  • D. C. Ralph and M. D. Stiles, “Spin Transfer Torques,” Journal of Magnetism and Magnetic Materials, vol. 320, issue 7, pp. 1190-1216, April 2008.

  • R. E. Simpson, et al., “Toward the Ultimate Limit of Phase Change in Ge2Sb2Te5,” Nano Letter, pp. 414-419, 2010.

  • Elaine Ou and S. Simon Wong, “Array Architecture for a Nonvolatile 3-Dimensional Cross-Point Resistance-Change Memory,” IEEE J. Solid-State Circuits, vol. 46, no. 9, pp. 2158-2170, Sep. 2011.

  • R. Stanley Williams, “How we found the missing memristor,” IEEE Spectrum, vol. 45, no. 12, pp. 28-35, 2008.

  • A. Kawahara, et al., “An 8Mb Multi-Layered Cross-Point ReRAM Macro With 443MB/s Write Throughput,” IEEE Journal of Solid-State Circuits, Vol. 48, No. 1, January 2013.

  • D. Niu, C. Xu, N. Muralimanohar, N. P. Jouppi, Y. Xie, “Design Trade-Offs for High Density Cross-Point Resistive Memory,” ISLPED, 2012, pp. 209-214.

  • M. Yoshimoto, et al., “A Divided Word-line Structure in the Static SRAM and Its Application to a 64K Full CMOS RAM” IEEE Journal of Solid-State Circuits, Vol. 18, No. 5, Oct. 1983.

  • P. Packan, et al., “High Performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors,” in Int. Electron Devices Meeting (IEDM) Tech. Dig. Papers, Dec. 2009, pp. 659-662.


  • Login