Lab 9 ASIC Logic. 第八組 R91943003 陳方玉 R91943007 陳建宏 R91943072 柯鴻洋 R89921022 吳佑焉. Outline. Introduction to the ASIC Logic Experiment Steps RGB to YUV Conversion HW Module. Outline. Introduction to the ASIC Logic Experiment Steps RGB to YUV Conversion HW Module.
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(1)Flash the LEDs on the Logic Module from left to right.
(2)The speed of flashing the LEDs from left to right can be
set by changing the configuration of the 8-way switch.
(3) Comparison of programming FPGA
FPGA version: programs the FPGA by writing the bit stream image into the FPGA directly. The image will start running right after programming into the FPGA.
Flash version: programs the FPGA by writing the bit stream image into the flash. The image will start after next power up of the development system.
Control Clock Frequency
by 8-Way Switches
Setting Clock Frequency
(1)Determine the DRAM size on the Core Module and set
up the system controller
(2)Make sure the Logic Module is present in the AP expansion
(3)Report module information
(4)Set the Logic Module clock frequencies
(5)Test SSRAM for word, halfword, and byte accesses
(6)Test the custom design device’s single register access
Flash the LED
(7)Remain in a loop that displays the 8-way switch value of the
Logic Modules on its LEDs.
These steps are the same as in experiment 8:
Remember to set the third switch on
Program FPGA from Image 0
(1)Add MYIP.v into top module.
Modification of AHBDecoder.v
Modification of AHBMuxS2M.v
Divide HWDATA into r,g,b parts
Combine y,u,v into output HRDATA
Write RGB value into LM_MYIP
and read YUV as data_myip
Post processor for data_myip
to read out YUV valueLogic.c
Set Registor for LM_MYIP
Result of Pure Software Implementation
Result of Hardware Implementation