Albert Yian Strategic Users Program Manager / Asia Pac

1. Artisan Components 2003 Great Solutions for The Complexity of SoC Designs Albert Yian Strategic Users Program Manager / Asia Pac ** Thanks to Scott Becker, Dhrumil Gandhi & Mike Brunolli

2. Overview • SoC Power issue / Solution • SoC Leakage issue / Solution • SoC Analog Issue / Solution • Summary

3. Meltdown

4. Rising Power • Clock Frequencies: 10MHz -> 10GHz • Transistor count: 1M -> 1B • Capacitance per mm2: 3x to 5x increase • Die Size growth has slowed from 1.14x/year • VDD scaling: 3.3V -> 1.0V => 10x reduction • Leakage power at chip level: 100x • Constrains VDD scaling

5. Ruff Stuff • Power is the main constraint for high performance • Costs of packaging, cooling • Reliability • Thermal effects • Power supply costs • Battery powered products rapidly growing • Power, power, power • Cost sensitive • No significant relief on performance

6. Stand Up • Co-operation between architecture, design, process, IP and EDA is must • C * V2 * f power management • Constrained by increased leakage currents • Voltage scaling • Faster transistors are also leakier • Parallelization • High K gate oxides • Many techniques commonly in use today to reduce C, V or f • Clock gating • Low-K • Standby modes

7. Artisan Solution Artisan products are designed for low power: • Gated clock cells • Low power XL cells, 2mA I/Os • Multi-Vt • Stage ratios designed to minimize crossbar currents • Transistor sizes and ratios optimized for maximum performance with minimum capacitance • Balanced clock drivers • Minimum loading on clock nodes for FFs • Densest cell layouts to reduce internal and wiring capacitances • Design flow support: power models, Multi-VDD characterization

8. Artisan Solution (Memory) • Memory standard features: • Self Timing • High density bit cells • Clock driver optimization • Standby mode • Mask write • Highly optimized architectures: • LP family • 2X power reduction • ULP • 4x-5x power reduction

9. is the major technical problem facing the semiconductor industry” “Power consumption, particularly off-state current leakage, – A. Grove, Intel, December 13, 2002

10. Background The drive to decrease power and increase performance creates the need to reduce device geometries and device threshold voltages Leakage • CMOS leakage < 180nm • Sub-threshold dominates but gate  as oxide thickness  • May be barrier to scaling • Is significant % of total power consumption at 90nm 54% 15 Present leakage total 42% 18% 4% 10 0% Switching Power trend 5 1.4x Sub-threshold leakage 0 0.01 0.1 1 Channel length (µm)

11. Impact of Leakage • Noise margin • Package complexity • Reliability • Design flows • Design automation support • Circuit design • Memory performance isn’t scaling with process • Analog • Testing • Performance vs. power

12. Memory Design Issues Bl Bl • Memory performance and functionality • Local variations can cause higher than predicted leakage • Offset in matched transistors cc0 Iread cc1 Ileak1 …... cc(n-1) Ileakn ccn Ileak(n-1)

13. Weak inversion current, drain induced barrier lowering, and narrow width effect Gate oxide tunneling Punch-through Reverse bias diode & gated diode Gate induced drain leakage (GIDL) Components of Leakage Gate Source Drain n + n + Bulk

14. -Vr S Sub-Threshold Leakage 1.0 0.8 0.6 • Leakage  exponentially as Vth is  • What happens to the drive current to leakage ratio? • Every 85mV decrease in Vth increases leakage current an order of magnitude • Short channel device threshold is proportional to device length Drain current (linear scale) 0.4 Vth 0.2 0 85 mV 1.0 0.1 0.01  Ioff 10 S ~ 85mV/decade (Log scale) 0.001 0.0001 10x IOFF 0.00001 0.000001 0 0.5 1.0 1.5 Gate voltage

15. Sub-Threshold Leakage - Continued • Leakage increases exponentially with temperature • Worst case leakage occurs at the hottest temperature and fastest process corner 1 0.1 Normalized sub-threshold current Worse case 0.01 sub-threshold current 0.001 -20 0 20 40 60 80 Temperature

16. Log l D D V t I V I D + D - D D 1/s I LD V + G - + V - I S L1 I L2 -V 0 V V s1 10 GS Sub-Threshold Leakage Reduction Techniques • Source biasing • Variable-threshold CMOS (VTCMOS) • Threshold partitioning Source: Kao, Narendra, Chandrakasan IEEE 2002

17. Sub-Threshold Leakage Reduction Techniques - Continued • Dual-threshold domino logic

18. 1.2 I 1.0 stack - l W l 0.8 I stack - u Normalized W Current u 0.6 0.4 V V dd dd 0.2 w I I u device stack-u 0 w V int 0 0.5 1.0 1.5 V (V) int w I l stack-l V x Sub-Threshold Leakage Reduction Techniques - Continued • Transistor stacking • Power supply gating • Power supply partitioning Source: Kao, Narendra, Chandrakasan IEEE 2002

19. Sub-Threshold Leakage Reduction Techniques - Continued • Multi-threshold CMOS (MTCMOS)

20. The Artisan Solution Standard Cells Multi-threshold libraries Longer channel lengths on slow path to reduce leakage Polynomial based timing and power models for design optimization • Memories • Memories with read to leak optimized timing • Multi-threshold periphery • Timing margins optimized with regard to process variation • Polynomial based timing and power models for design optimization • Analog • Please see Mike B. in SoC Analog

21. Graphics Processors Communications & RF Interface Data Acquisition and Conversion Audio Controllers The World is Analog …… ……Digital electronics is just the transit medium for analog experiences.

22. SoC Analog • Trends • Mixed Signal – Component of IC Design • Choosing Integration and Technology Strategy • Adoption of Mixed Signal Technology • Design Challenges • Affecting Developers • Affecting Integrators • Solutions • Favorable Analog Integration • Artisan Mixed-Signal Solutions

23. Mixed Signal – Major Component of IC Design Analog Timing Functions 5 to10% of Chip Area I/O and High Speed Communications Functions 20 to 30% of Chip Area Standard Cells 25 to 45% of Chip Area Embedded Memories 40 to 60% of Chip Area

24. Interface CMOS Large Signal Analog Exotic Technologies Data Conversion BiCMOS Choosing Integration & Technology Strategy GAIN/SIGNAL CONDITIONING A/D FILTER GAIN/SIGNAL CONDITIONING A/D CPU DSP PLL INTERFACE MEM GAIN/SIGNAL CONDITIONING D/A FILTER GAIN/SIGNAL CONDITIONING D/A

25. Analog IP is essential for Convergence of Digital and Analog in SoC design • Explosive growth of Mixed-Signal SoCs • Growth of SoC with M/S: 20% in 2001 to 70% in 2006 Companies lack expertise, resources and analog tool infrastructure

26. Design Challenges Affecting Developers • Reduced Supply Voltage • Limited dynamic range • Loss of proven techniques • Noise considerations

27. - Clock Multiplication, - Deskewing or - Clock Recovery Loop Configuration - Low tracking jitter - Period jitter filtering & low freq. overshoot Loop Dynamics - Counter Resetting - Lock or Cycle Slip Detector - Testing Circuitry - Multiple or adjustable output phases Options Design Challenges Affecting Integrators Matching Specification and Expertise - Wide VCO Frequency Range or - Low Phase Noise Circuit Structure

28. Design Challenges Affecting Integrators • Keeping the Performance • Clock distribution adds jitter • Attention to package consideration • for cross talk and noise • Grounding • Multiple domains require solid ground • Attention to reference when crossing power domains

29. Artisan Solution - Mixed Signal IP Analog IP Specialty I/Os Interface PHYs DDRI - DDRII – GDDRII,….etc. Deskew PLL HSTL SSTL2 & 3 Multiplier PLL LVDS Deskew DLL PCI & PCI X CDR PLL AGP 4X & 8X D/A Converters PECL Bandgaps GMII, RGGMII

30. Summary Artisan is ready to help you ! Please visit Artisan’s website at www.artisan.com Thank you!