Wireless Body Area Network

1. Wireless Body Area Network

2. MSP430F2013: 2KB + 256B Flash Memory128B RAM

3. MSP430MSP (mixed signal processor) • The CPU is small and eficient, with a large number of registers. • It is extremely easy to put the device into a low-power mode. No specialinstruction is needed: The mode is controlled by bits in the status register. TheMSP430 is awakened by an interrupt andreturns automatically to its low-powermode after handling the interrupt. • There are several low-power modes, depending on how much of the device shouldremain active and how quickly it should return to full-speed operation. • There is a wide choice of clocks. Typically, a low-frequency watch crystal runscontinuously at 32 KHz and is used to wake the device periodically. The CPU is clocked by an internal, digitally controlled oscillator (DCO), which restarts in less than 1μs in the latest devices. Therefore the MSP430 can wake from a standbymode rapidly, perform its tasks, and return to a low-power mode.

4. MSP430 • •A wide range of peripherals is available, many of which can run autonomously without the CPU for most of the time. • Many portable devices include liquid crystal displays, which the MSP430 can drive directly. • Some MSP430 devices are classed as application-specific standard products(ASSPs) and contain specialized analog hardware for various types ofmeasurement.

5. Παράδειγμα ζυγαριάς

6. MSP430 FEATURES • There is a wide choice of clocks. Typically, a low-frequency watch crystal runscontinuously at 32 KHz and is used to wake the device periodically. The CPU isclocked by an internal, digitally controlled oscillator (DCO), which restarts in lessthan 1μs in the latest devices. Therefore the MSP430 can wake from a standby mode rapidly, perform its tasks, and return to a low-power mode. • A wide range of peripherals is available, many of which can run autonomously without the CPU for most of the time. • Many portable devices include liquid crystal displays, which the MSP430 can drive directly. • Some MSP430 devices are classed as application-specific standard products (ASSPs) and contain specialized analog hardware for various types ofmeasurement.

7. MSP430F2013

8. MSP430F2013και πηγές ρολογιών

10. SERVOS AND PWM

11. MSP430F2013 • VCC and VSS are the supply voltage and ground for the whole device (the analogand digital supplies are separate in the 16-pin package). • P1.0–P1.7, P2.6, and P2.7 are for digital input and output, grouped into ports P1and P2. • TACLK, TA0, and TA1 are associated with Timer_A; TACLK can be used as theclock input to the timer, while TA0 and TA1 can be either inputs or outputs. Thesecan be used on several pins because of the importance of the timer. • A0-, A0+, and so on, up to A4±, are inputs to the analog-to-digital converter. Ithas four differential channels, each of which has negative and positive inputs. • VREF is the reference voltage for the converter. • ACLK and SMCLK are outputs for the microcontroller’s clock signals. These canbe used to supply a clock to external components or for diagnostic purposes. • SCLK, SDO, and SCL are used for the universal serial interface, which • communicates with external devices using the serial peripheral interface (SPI) orinter-integrated circuit (I2C) bus. • XIN and XOUT are the connections for a crystal, which can be used to provide anaccurate, stable clock frequency. • RST is an active low reset signal. Active low means that it remains high near VCCfor normal operation and is brought low near VSS to reset the chip. Alternativenotations to show the active low nature are _RST and /RST. • NMI is the nonmaskable interrupt input, which allows an external signal tointerrupt the normal operation of the program. • TCK, TMS, TCLK, TDI, TDO, and TEST form the full JTAG interface, used toprogram and debug the device. • SBWTDIO and SBWTCK provide the Spy-Bi-Wire interface, an alternative to theusual JTAG connection that saves pins.

13. Τεχνικές λεπτομέρειες…. • These devices have flash memory, 1KB in the F2003 or 2KB in the F2013, and 128 bytes of RAM. • Six blocks are shown for peripheral functions (there are many more in larger devices). All MSP430s include input/output ports, Timer_A, and a watchdog timer, although the details differ. The universal serial interface (USI) and sigma–delta analog-to-digital converter (SD16_A) are particular features of this device. • The brownout protection (διακοπή ρεύματος) comes into action if the supply voltage drops to a dangerous level. Most devices include this but not some of the MSP430x1xxfamily. • There are ground and power supply connections. Ground is labeled VSS and is taken to define 0V. The supply connection is VCC. For many years, the standard for logic was VCC =+5V but most devices now work from lower voltages and a range of 1.8–3.6V is speci.ed for the F2013. The performance of the device depends on VCC. For example, it is unable to program the .ash memory if VCC < 2.2V and the maximum clock frequency of 16MHz is available only if VCC ≥ 3.3V.

14. Clock Generator • A fast clock to drive the CPU, which can be started and stopped rapidly to conserve energy but usually need not be particularly accurate. • A slow clock that runs continuously to monitor real time, which must therefore use little power and may need to be accurate.

15. Clock Generator • An integrated high-speed digitally controlled oscillator (DCO) can source the master clock (MCLK) used by the CPU and high-speed peripherals. By design, the DCO is active and stable in less than 2 µs at 1 Mhz. • MSP430-based solutions effectively use the high-performance 16-bit RISC • CPU in very short bursts.

16. Clock Generator • Crystal: Accurate (the frequency is close to what it says on the can, typically within 1 part in 105) and stable (does not change greatly with time or temperature). Crystals for microcontrollers typically run at either a high frequency of a few MHz to drive the main bus or a low frequency of 32,768 Hz for a real-time clock. The disadvantages are that crystals are expensive and delicate, the oscillator draws a relatively large current, particularly at high frequency, and the crystal is an extra component and may need two capacitors as well. Crystal oscillators also take a long time to start up and stabilize,often around 105 cycles, which is an unavoidable side effect of their high stability. • Resistor and capacitor (RC): Cheap and quick to start but used to have poor accuracy and stability. The components can be external but are now more likely to be integrated within the MCU. The quality of integrated RC oscillators has improved dramatically in recent years and the F20xx provides four frequencies calibrated at the factory towithin ±1%.

17. Clock System • Master clock, MCLK is used by the CPU and a few peripherals. • Sub-system master clock, SMCLK is distributed to peripherals. • •Auxiliary clock, ACLK is also distributed to peripherals.

18. Clock System

19. Clock System • Low- or high-frequency crystal oscillator, LFXT1: Available in all devices. It is usually used with a low-frequency watch crystal (32 KHz) but can also run with a high-frequency crystal (typically a few MHz) in most devices. An external clock signal can be used instead of a crystal if it is important to synchronize the MSP430 with other devices in the system. • High-frequency crystal oscillator, XT2: Similar to LFXT1 except that it is restricted to high frequencies. It is available in only a few devices and LFXT1 (or VLO) is used instead if XT2 is missing. • Internal very low-power, low-frequency oscillator, VLO: Available in only the more recent MSP430F2xx devices. It provides an alternative to LFXT1 when the accuracy of a crystal is not needed. • Digitally controlled oscillator, DCO: Available in all devices and one of the highlights of the MSP430. It is basically a highly controllable RC oscillator that starts in less than 1 s in newer devices.

20. Clock System • ACLK comes from a low-frequency crystal oscillator at 32 KHz. There is no choice in almost all devices, the exceptions being those with a VLO. • Both MCLK and SMCLK are supplied by the DCO with a frequency of around 1 MHz. This is stabilized by the FLL where present. You may wish to raise this frequency provided that VCC is high enough to support it.

21. EZ-430 • ACLK δεν είναι συνδεδεμένο σε κρύσταλλο 32 kHz στο ΕΖ430

22. Μετρητές (Timers) του MSP430F2013 • 1. Watchdog timer. Η κύρια λειτουργία του watchdog καταχωρητή είναι στο να προφυλάσσει το σύστημα από ανεπιθύμητη λειτουργία με το να το επαναφέρει μετά από καθορισμένο χρόνο. Μπορεί να χρησιμοποιηθεί και ως μετρητής χρονικών διαστημάτων, αν η προηγούμενη λειτουργία του δεν είναι επιθυμητή. • 2. Timer_A. Τυπικά ο καταχωρητής αυτός έχει τρία κανάλια, μπορεί να χειριστεί εξωτερικές εισόδους να μετρήσει συχνότητα και να οδηγήσει εξόδους σε καθορισμένους χρόνους είτε μία φορά είτε περιοδικά. Επειδή έχει εσωτερικές συνδέσεις με άλλα τμήματα του ολοκληρωμένου μπορούμε να τον χρησιμοποιήσουμε για να μετρήσουμε τη διάρκεια ενός σήματος από το ένα τμήμα στο άλλο για παράδειγμα. Μπορεί επίσης να παράγει διακοπές (interrupts).

23. Timer A

24. Timer A • Timer_A clock source select, TASSELx: There are four options for the clock: the • internal SMCLK or ACLK or two external sources.We use SMCLK because it is • always available, which needs TASSELx = 10. • Input divider, IDx: The frequency of the clock can be divided before it is applied to the • timer, which extends the period of the counter.We use the maximum factor of eight, • which needs IDx = 11. • Mode control, MCx: The timer has four modes. By default it is off to save power.We • .rst use the simplest Continuous mode, in which TAR simply counts up through its full • range of 0x0000–0xFFFF and repeats. This needs MCx = 10. • Timer_A clear, TACLR: Setting this bit clears the counter, the divider, and the • direction of the count (it can go both up and down in up/down mode). The bit is • automatically cleared by the timer after use. It is usually a good idea to clear the counter • whenever the timer is recon.gured to ensure that the .rst period has the expected • duration. • Timer_A interrupt enable, TAIE: Setting this bit enables interrupts when TAIFG • becomes set.We do not use this. • Timer_A interrupt .ag, TAIFG: This bit can be modi.ed by the timer itself or by a • program. It is raised (set) by the timer when the counter becomes 0. In continuous mode • this happens when the value in TAR rolls over from 0xFFFF to 0x0000. An interrupt is • also requested if TAIE has been set. The program must clear TAIFG so that the next • over.ow can be distinguished.

25. Timer A • Timer block: The core, based on the 16-bit register TAR. There is a choice of sourcesfor the clock, whose frequency can be divided down (prescaled). The timer block has nooutput but a flag TAIFG is raised when the counter returns to 0. • Capture/compare channels: In which most events occur, each of which is based on aregister TACCRn. They all work in the same way with the important exception ofTACCR0. Each channel can • Capture an input, which means recording the “time” (the value in TAR) atwhich the input changes in TACCRn; the input can be either external or internalfrom another peripheral or software. • Compare the current value of TAR with the value stored in TACCRn andupdate an output when they match; the output can again be either external orinternal. • Request an interrupt by setting its flag TACCRn CCIFG on either of theseevents; this can be done even if no output signal is produced. • Sample an input at a compare event; this special feature is particularly useful if Timer_A is used for serial communication in a device that lacks a dedicated interface.

26. Timer A • The number of channels is sometimes appended to the name as in Timer_A3. • Capture/compare channel 0 is special intwo ways. Its register TACCR0 is taken over for the modulus value in Up and Up/Downmodes, so that it is no longer available for its usual functions. It also has its owninterrupt vector with a higher priority than the other interrupts from Timer_A, which allshare a common vector. Therefore channel 0 should be chosen for the most urgent tasks if itis free.

27. Timer A

28. Timer A

29. Timer_A Counting Modes The timer has four modes of operation, selected with the MCx bits: • Stop (MC = 0): The timer is halted. All registers, including TAR, retain their values sothat the timer can be restarted later where it left off. • Continuous (2): The counter runs freely through its full range from 0x0000 to 0xFFFF,at which point it over.ows and rolls over back to 0. The period is 216 = 65,536 counts.This mode is most convenient for capturing inputs and is also used when channelsprovide outputs with different frequencies or that are not periodic at all. • Up (1): The counter counts from 0 up to the value in TACCR0, the capture/compareregister for channel 0. It returns to 0 on the next clock transition. The period is(TACCR0+1) counts. For example, if TACCR0 = 4, the sequence of counts is 0, 1, 2,3, 4, 0, 1, . . . with period 5. Up mode is usually used when all channels provide outputsat the same frequency, often for pulse-width modulation. • Up/Down (3): The counter counts from 0 up to TACCR0, then down again to 0 andrepeats. The period is 2ΧTACCR0 counts. For example, if TACCR0=3, the sequenceof counts is 0, 1, 2, 3, 2, 1, 0, 1, . . . with period 6. This is a specialized mode, typicallyused for centered pulse-width modulation.

30. Timer_A Counting Modes UP/DOWN Mode Timer counts between 0 and CCR0 and 0 Stop/Halt Mode Timer is halted with the next +CLK UP Mode Timer counts between 0 and CCR0 Continuous Mode Timer continuously counts up 0FFFFh CCR0 0h

31. rw- rw- rw- rw- rw- rw- rw- rw- rw- rw- rw- rw- rw- (w)- rw- rw- (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) 0 0 Stop Mode 0 1 Up Mode 1 0 Continuous Mode 1 1 Up/Down Mode 0 0 1/1, Pass 0 1 1/2 1 0 1/4 1 1 1/8 Timer_A 16-bit Counter 15 0 TACTL Input Input Mode un- TAIE TAIFG unused CLR Select Divider Control used 160h MC1 MC0 ID1 ID0 SSEL1 SSEL0 0 0 TACLK ACLK 0 1 1 0 MCLK 1 1 INCLK

32. Timer_A 16-bit Control Register

33. Timer_A 16-bit Control Register • Three items are given for each bit: • Its position in the word, which should not be needed • Its name, which is defined in the header file and should be known to the debugger; • some bits are not used, which I show by a gray fill. • The accessibility and initial condition of the bit; here they can all be read andwritten with the exception of TACLR, where the missing r indicates that there is nomeaningful value to read. The (0) shows that each bit is cleared after a power-onreset (POR).

34. Timer A • The flag TAIFG in TACTL is set when the timer counts to 0 and a maskable interrupt isrequested if the TAIE bit is set.The family user’s guidealways shows count in italics to emphasize that actions such as setting TAIFG occur onlyas a result of normal counting. They do not occur if the appropriate value is writtendirectly to a register. For example, setting TACLR clears TAR but does not set TAIFG.

35. Timer_A Capture Compare Blocks Overflow x Logic Timer Bus COVx Data Bus Capture Path CMPx CCISx1 CCISx0 0 CCIxA 15 0 1 CCIxB 1 Capture 2 Capture/Compare Register CCRx GND Mode 3 Capture Timer VCC 0 Clock Synchronize CCMx1 CCMx0 SCSx Capture 0 0 Disabled 0 1 Pos. Edge 15 1 0 Neg. Edge 0 1 1 Both Edges Comparator x to Port0 CAPx EQUx 0 1 Set_CCIFGx Compare Path EN Y SCCIx A CCIx CCRx 15 0 0172h 15 0 to 2 2 017Eh rw- rw- rw- rw- rw- rw- rw- rw- rw- rw- rw- rw- rw- rw- rw- rw- (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) 15 0 CCTLx un- CAPTURE INPUT CAP OUTMODx CCIFG SCS CCIE SCCI CCI OUT COV MODE SELECT used 162h to rw- rw- rw- rw- rw- rw- rw- rw- rw- rw- rw- rw- r rw- rw- rw- 16Eh (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0)

36. Capture/Compare Channels • The central feature of each channel is itscapture/compare register TACCRn • In Capturemode this stores the “time”—the value in TAR—at which an event occurs on the input; • InCompare mode it specifies the time at which the output should next be changed and aninterrupt requested. The mode is selected with the CAP bit. This is cleared by default sothat the channel is in Compare mode. Any mixture of capture and compare channels can beused and the mode can be switched freely from one to the other.

40. Interrupts from Timer_A

41. OMx2 OMx1 OMx0 Function Operational Conditions Output Mode Outx signal is set according to Outx bit 0 0 0 0 0 Set EQUx sets Outx signal clock synchronous with timer clock 1 0 PWM Toggle/Reset EQUx toggles Outx signal, reset with EQU0, clock sync. with timer clock 0 1 0 1 1 PWM Set/Reset EQUx sets Outx signal, reset with EQU0, clock synchronous with timer clock Toggle EQUx toggles Outx signal, clock synchronous with timer clock 1 0 0 1 0 Reset EQUx resets Outx signal clock synchronous with timer clock 1 0 PWM Toggle/Reset EQUx toggles Outx signal, set with EQU0, clock synchronous with timer clock 1 1 1 1 1 PWM Set/Reset EQUx resets Outx signal, set with EQU0, clock synchronous with timer clock Timer_A Output Units Timer Clock TAx OUTx (CCTLx.2) EQUx Logic Output Signal Outx Set Output D Q EQU0 To Output Logic TAx Timer Clock Reset POR Output Mode 0 OUTx OMx2 OMx1 OMx0

43. 0FFFh 0h CCR0: TA0 Input Px.x Capture Mode: Positive Edge CCR1: TA1 Input Px.y Capture Mode: Both Edges CCR2: TA2 Input Px.z Capture Mode: Negative Edge CCR0 CCR0 CCR1 CCR1 CCR1 CCR1 CCR1 CCR1 Interrupts can be generated CCR2 Timer_A Continuous-Mode Example Example shows three independent HW event captures. CCRx “stamps” time of event - Continuous-Mode is ideal.

44. 0FFFFh CCR0 CCR1 CCR2 0h TA1 Output CCR1: PWM Set/Reset Px.x CCR2: PWM Reset/Set TA2 Output Px.y CCR0: PWM Toggle TA0 Output Px.z EQU2 EQU2 EQU2 EQU1 EQU0 EQU0 EQU1 EQU0 Interrupts can be generated Timer_A PWM Up-Mode Example Auto Re-load Output Mode 4: PWM Toggle Example shows three different asymmetric PWM-Timings generated with the Up-Mode

45. 0FFFFh t hlfper CCR0 CCR2 CCR1 CCR3 0h TA1 Output 0 Degrees (0.5xVmotor) Px.x t pw1 TA2 Output +120 Degrees t Px.y pw2 (0.93xVmotor) t pw3 TA0 Output -120 Degrees Px.z (0.07xVmotor) Interrupts can be generated TIMOV EQU0 TIMOV EQU0 TIMOV Timer_A PWM Up/Down Mode Example Example shows Symmetric PWM Generation - Digital Motor Control

46. C Examples, CCR0 Continuous mode ISR, TA_0 ISR //*************************************************************** // MSP-FET430P140 Demo - Timer_A Toggle P1.0, // CCR0 Contmode ISR, DCO SMCLK // Description; Toggle P1.0 using software and TA_0 ISR. Toggle rate is // set at 50000 DCO/SMCLK cycles. Default DCO frequency used for TACLK. // Durring the TA_0 ISR P0.1 is toggled and 50000 clock cycles are added to // CCR0. TA_0 ISR is triggered exactly 50000 cycles. CPU is normally off and // used only durring TA_ISR. // ACLK = n/a, MCLK = SMCLK = TACLK = DCO~ 800k // // // MSP430F149 // --------------- // /|\| XIN|- // | | | // --|RST XOUT|- // | | // | P1.0|-->LED // // M. Buccini // Texas Instruments, Inc // September 2003 // Built with IAR Embedded Workbench Version: 1.26B // December 2003 // Updated for IAR Embedded Workbench Version: 2.21B //********************************************************************** #include <msp430x14x.h> void main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop WDT P1DIR |= 0x01; // P1.0 output CCTL0 = CCIE; // CCR0 interrupt enabled CCR0 = 50000; TACTL = TASSEL_2 + MC_2; // SMCLK, contmode _BIS_SR(LPM0_bits + GIE); // Enter LPM0 w/ interrupt } // Timer A0 interrupt service routine interrupt[TIMERA0_VECTOR] void TimerA(void) { P1OUT ^= 0x01; // Toggle P1.0 CCR0 += 50000; // Add Offset to CCR0 }

47. C Examples, CCR1 Contmode ISR, TA_1 #include <msp430x14x.h> void main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop WDT P1DIR |= 0x01; // P1.0 output CCTL1 = CCIE; // CCR1 interrupt enabled CCR1 = 50000; TACTL = TASSEL_2 + MC_2; // SMCLK, Contmode _BIS_SR(LPM0_bits + GIE); // Enter LPM0 w/ interrupt } // Timer_A3 Interrupt Vector (TAIV) handler #pragma vector=TIMERA1_VECTOR __interrupt void Timer_A(void) { switch( TAIV ) { case 2: // CCR1 { P1OUT ^= 0x01; // Toggle P1.0 CCR1 += 50000; // Add Offset to CCR1 } break; case 4: break; // CCR2 not used case 10: break; // overflow not used } } //***************************************************************** // MSP-FET430P140 Demo – // Timer_A Toggle P1.0, CCR1 Contmode ISR, CO SMCLK // Description; Toggle P1.0 using using software and TA_1 ISR. // Toggle rate is set at 50000 DCO/SMCLK cycles. // Default DCO frequency used for TACLK. // Durring the TA_1 ISR P0.1 is toggled and // 50000 clock cycles are added to CCR1. // TA_1 ISR is triggered exactly 50000 cycles. // CPU is normally off and used only durring TA_ISR. // ACLK = n/a, MCLK = SMCLK = TACLK = DCO ~ 800k // Proper use of TAIV interrupt vector generator demonstrated. // // MSP430F149 // --------------- // /|\| XIN|- // | | | // --|RST XOUT|- // | | // | P1.0|-->LED // // M. Buccini // Texas Instruments, Inc // September 2003 // Built with IAR Embedded Workbench Version: 1.26B // December 2003 // Updated for IAR Embedded Workbench Version: 2.21B //**************************************************************

48. C Examples, PWM, TA1-2 upmode //*************************************************************************** // MSP-FET430P140 Demo - Timer_a PWM TA1-2 upmode, DCO SMCLK // // Description; This program will generate a two PWM outputs on P1.2/1.3 using // Timer_A in an upmode. The value in CCR0, defines the period and the // values in CCR1 and CCR2 the duty PWM cycles. Using ~ 800kHz SMCLK as TACLK, // the timer period is ~ 640us with a 75% duty cycle on P1.2 and 25% on P1.3. // ACLK = na, SMCLK = MCLK = TACLK = default DCO ~ 800kHz. // // MSP430F149 // ----------------- // /|\| XIN|- // | | | // --|RST XOUT|- // | | // | P1.2|--> CCR1 - 75% PWM // | P1.3|--> CCR2 - 25% PWM // // M.Buccini // Texas Instruments, Inc // September 2003 // Built with IAR Embedded Workbench Version: 1.26B // January 2004 // Updated for IAR Embedded Workbench Version: 2.21B //***************************************************** void main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop WDT P1DIR |= 0x0C; // P1.2 and P1.3 output P1SEL |= 0x0C; // P1.2 and P1.3 TA1/2 options CCR0 = 512-1; // PWM Period CCTL1 = OUTMOD_7; // CCR1 reset/set CCR1 = 384; // CCR1 PWM duty cycle CCTL2 = OUTMOD_7; // CCR2 reset/set CCR2 = 128; // CCR2 PWM duty cycle TACTL = TASSEL_2 + MC_1; // SMCLK, up mode _BIS_SR(LPM0_bits); // Enter LPM0 }

49. C Examples, CCR0 Upmode ISR, TA_0 //************************************************************************ // MSP-FET430P140 Demo - Timer_A Toggle P1.0, CCR0 upmode ISR, 32kHz ACLK // // Description; Toggle P1.0 using software and the TA_0 ISR. Timer_A is // configured in an upmode, thus the the timer will overflow when TAR counts // to CCR0. In this example, CCR0 is loaded with 1000-1. // Toggle rate = 32768/(2*1000) = 16.384 // ACLK = TACLK = 32768, MCLK = SMCLK = DCO~ 800k // //*An external watch crystal on XIN XOUT is required for ACLK*// // // MSP430F149 // --------------- // /|\| XIN|- // | | | 32kHz // --|RST XOUT|- // | | // | P1.0|-->LED // // M. Buccini // Texas Instruments, Inc // October 2003 // Built with IAR Embedded Workbench Version: 1.26B // December 2003 // Updated for IAR Embedded Workbench Version: 2.21B //************************************************************************ #include <msp430x14x.h> void main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop WDT P1DIR |= 0x01; // P1.0 output CCTL0 = CCIE; // CCR0 interrupt enabled CCR0 = 1000-1; TACTL = TASSEL_1 + MC_1; // ACLK, upmode _BIS_SR(LPM3_bits + GIE); // Enter LPM3 w/ interrupt } // Timer A0 interrupt service routine #pragma vector=TIMERA0_VECTOR Interrupt[TIMERA0_VECTOR] void Timer_A (void) { P1OUT ^= 0x01; // Toggle P1.0 }

50. Simple PWM program (davies) • // simppwm1.c - Simple, slow PWM using Timer_A in Up mode from ACLK • // Period = 1s, LED1 at duty cycle D = 1/2, LED2 at D = 1/4 • // Olimex 1121STK, LED1 on P2.3 = TA1, LED2 on P2.4 = TA2, active low • // J H Davies, 2007-07-17; IAR Kickstart version 3.42A • //---------------------------------------------------------------------- • #include <io430x11x1.h> // Specific device • #include <intrinsics.h> // Intrinsic functions • //---------------------------------------------------------------------- • void main (void) • { • WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer • // Configure ports 1 and 2; redirect P2.3,4 to Timer_A • P1OUT = BIT0 | BIT1; // Output high for Freq pin and TXD • P1DIR = BIT0 | BIT1; • P2SEL = BIT3 | BIT4; // Re-route P2.3 to TA1, P2.4 to TA2 • P2DIR = BIT0 | BIT3 | BIT4 | BIT5; // Piezo and LED outputs • // Set up Timer_A for PWM on active low LEDs, channels 1 and 2 • TACCR0 = 0x7FFF; // 1s period from 32KHz timer clock • TACCR1 = 0x4000; // Duty cycle D = 1/2 • TACCR2 = 0x2000; // Duty cycle D = 1/4 • TACCTL1 = OUTMOD_3; // Set/reset mode for negative PWM • TACCTL2 = OUTMOD_3; // Set/reset mode for negative PWM • // Start timer from ACLK, no division, Up mode, clear, no interrupts • TACTL = TASSEL_1 | ID_0 | MC_1 | TACLR; • for (;;) { // Loop forever • __low_power_mode_3(); // Remain in LPM3, CPU not needed! • } // (nor are interrupts) • }