A VHDL nyelv alapjai

1. A VHDL nyelv alapjai VHDL nyelvi elvonatkoztatások Tervezési hierarchiák – szerkezeti leírás

2. VHDL nyelvi elemek VHDL is composed of language building blocks that consist of more than 75 reserved words and about 200 descriptive words or wordcombinations

3. ABSACCESSAFTERALIASALLANDARCHITECTUREARRAYASSERTATTRIBUTE BEGINBLOCKBODYBUFFERBUS CASECOMPONENTCONFIGURATION CONSTANT DISCONNECTDOWNTO ELSEELSIFENDENTITYEXIT FILEFORFUNCTION GENERATEGENERICGROUPGUARDED IFIMPURE ININERTIALINOUTIS LABELLIBRARYLINKAGELITERALLOOP MAPMOD NANDNEWNEXTNORNOTNULL OFONOPENOROTHERSOUT PACKAGEPORTPOSTPONEDPROCEDUREPROCESSPURE RANGERECORDREGISTERREMREPORTROLROR RETURN SELECTSEVERITYSIGNALSHAREDSLASLLSRASRLSUBTYPE THENTOTRANSPORTTYPE UNAFFECTEDUNITSUNTILUSE VARIABLE WAITWHENWHILEWITH XNORXOR Foglalt VHDL kulcsszavak

4. Tervleírási módszerek • Szerkezeti leírási módszer • Viselkedési leírási módszer • Adatáramlási leírási módszer • These two are similar in that both use a process to describe the functionality of a circuit Kapcsolási rajz

5. VHDL nyelvi elvonatkoztatások • VHDL is rich in language abstractions, in addition to which the language can be used to describe different abstraction levels, from functions right down to a gate description • Abstraction levels are a means of concealing details

6. Elvonatkoztatási szintek A fő témánk • Functional (system) level + architecture => • Behavioral level + resource handler => • RTL (dataflow) level + construction data => • Structural level + technology data => • Logic (gate) level + electrical specification => • Electrical level + layout requirements => • Layout level

7. A leírási módszerek meghatározásai • Szerkezeti leírási módszer:expresses the design as an arrangement of interconnected components • It is basically schematic • Viselkedési leírási módszer:describes the functional behavior of a hardware design in terms of circuits and signal responses to various stimuli • The hardware behavior is described algorithmically • Adatáramlási leírási módszer:is similar to a register-transfer language • This method describes the function of a design by defining the flow of information from one input or register to another register or output

8. Feladatköri (rendszer-) szint • Algorithms can be describe at this level • E.g. a controller algorithm can be described and simulated on the computer • An algorithm does not need to contain any time information • Specifications written in VHDL will be able to be simulated

9. Viselkedési szint • Behavior and time are described at this level • No architecture is required here • The advantage of models at this level is that models for simulation can be built quickly • A behavioral model can be described as functional modules and an interface interface between them • The modules contain one or more functions and time relations • In certain cases the architecture can be defined

10. Leírási módszerek összehasonlítása ABehavioral Descriptionuses a small number of processes where each process performs a number of sequential signal assignments to multiple signals In contrast, a Data-Flow Descriptionuses a large number of concurrent signal assignment statements A concurrent statement executes asynchronously with respect to other concurrent statements Concurrent statements used in Data-Flow Descriptioninclude:- block statement (used to group one or more concurrent statements)- concurrent procedure call- concurrent assertion statement- concurrent signal assignment statement

11. RTL = Regiszter átviteli szint • It consists of a language which describes behavior in • asynchronous and synchronous state machines • data paths • operators (+,*,<,>,...) • registers

12. Elektromos szint • Other name is: transistor level • There are models of • transistors • capacitances • resistances • This is not supported in VHDL

13. Layout szint • At layout level models are made of the physical process • This is not supported in VHDL

14. Szintézis = Növekvőösszetettség • Synthesis is done between each level • The volume of information increases between the various abstraction levels • E.g. technology information is required to synthesize from RT to gate level • Each transition (synthesis) generates more information • In order to implement a function in an ASIC, are required the followings: • technology information • wiring information • gate information • set-up times

15. Miért használnak különböző elvonatkoztatási szinteket? • It is usually the requirements that determine the abstraction level at which the information is to be described • If a short development time is required, a high abstraction level should be chosen as the description language • In practice RT level (and parts of behavioral) can be synthesized automatically to gate level

16. Különböző alkalmazások • ASIC = Application Specific Integrated Circuit • Usually includes FPGA, gate array, standard cell and full custom designs. • PCB = Printed Circuit Board design • On a circuit board there are usually several ASICs together with a microprocessor and its infrastructure • System = a number of PCBs

17. Modell kiértékelés • The code for VHDL component can be verified functionally in a simulator • The simulator simulates (“executes”) the VHDL code with input signals and produces a signal diagram and error messages on the basis of the components • The input signals are defined either in VHDL or in the simulator’s language • When the VHDL code is simulated, functional verification takes place • At a later stage, time verification of the design is also possible

18. Szimuláció • Simulating models is an effective way of verifying the design • The model in the computer is only a time-discrete model, however, while reality is continuous • The computer model is more or less like reality • It is least like reality at a high abstraction level (behavioral) and most like it at the lowest level (layout)

19. Egyéb elektronikai leíró nyelvek • There are several languages which are used to describe electronic designs • One popular language is called VERILOG • It is used from RT level down • In some other languages there are no hierarchies, which causes major problems when working on complex assignments • There languages are developed by universities and research centers

20. Other HDL languages • There are several other language extensions built to either aid in RTL construction or assist in modeling: • ParaCore - http://www.dilloneng.com/paracore.shtml • RubyHDL - http://www.aracnet.com/~ptkwt/ruby_stuff/RHDL/index.shtml • MyHDL - http://jandecaluwe.com/Tools/MyHDL/Overview.shtml • JHDL - http://www.jhdl.org/ • Lava - http://www.xilinx.com/labs/lava/ • HDLmaker - http://www.polybus.com/hdlmaker/users_guide/ • SystemC • AHDL – http://www.altera.com • It is goodfor Altera-made chips only, which limits its usefulness • But it is easy to pick up anduse successfully • The main purpose of a language -- programming, hdl, or otherwise -- is to ease the expression of design

21. A SystemC • C++ könyvtár rendszerszintű modellezésre • Különböző elvonatkoztatási szinteket támogat • Feladatköri leírástól RTL szintűig • Használható gyors, hatékony tervekhez • Igazoláshoz (verification)

22. Miért nem csak C++? • C++: sorrendi programozás, nem alkalmas párhuzamos események modellezésére • A hardver modellben kell késleltetés, idő • A hardver modellek közlési csatornái (port, signal) különböznek a szoftver modellekben használtaktól • C++ adattípusai túl távol állnak a hardver megvalósításoktól • C++ önmagában nem elég leírni egy bonyolult rendszert

23. SystemC adattípusok • Adattípusokat határoz meg a hardver modellezéshez • bit (‘0’, ‘1’) • bitvector (‘0101’) • logic (‘0’, ‘1’, ‘Z’, ‘X’) • logicvector (’01XZ’) • Használhatók az alap C++ adattípusok is • fixed • float • signed, unsigned, stb.

24. Verilog • Verifying Logic • Phil Moorby from Gateway Design Automation in 1984 to 1987 • Absorbed by Cadence • Cadence's ownership of Verilog => others support VHDL • Verilog-XL simulator from GDA in 1986 • Synopsis Synthesis Tool in 1988 • In 1990 became open language • OVI: Open Verilog International • IEEE Standard in 1995 • IEEE Std-1364-1995 • Last revision in 2001 • IEEE Std-1364-2001 • Ongoing work for adding • Mixed-signal constructs: Verilog-AMS • System-level constructs: SystemVerilog

25. VHDL vs. Verilog

26. VHDL vs. Verilog (Cont.) • It does seem that Verilog is easier for designing at the gate-level, but that people who do higher level simulations express a preference for VHDL • VHDL places constraints on evaluation order that limit theoptimizations that can be performed • Verilog allows the simulatorgreater freedom • For example, multiple levels of zero-delay gatescan be collapsed into a single super-gate evaluation in Verilog • VHDL requires preserving the original number of delta cycles of delayin propagating through those levels

27. VHDL vs. Verilog: Process block • VHDL: process (siga, sigb) begin …... end; • Verilog: always @ (siga or sigb) begin …. end

28. VHDL vs. Verilog:Concurrent Signal Assignment • VHDL: c <= a and b; • Verilog: assign c = a & b ;

29. VHDL vs. Verilog: Signal Delays • VHDL: a <= transport b after 1 ns; • Verilog: #1 assign a = b; • ‘a’ output is delayed by 1 time unit • The ‘# ‘ operator is the delay operator • # N will delay forN simulation units • Delays can assigned to both inputsand outputs #1 assign a = #1 b; • ‘b’ is delayed by 1 unit, then assigned to ‘a’, which is thendelayed by 1 time unit

30. VHDL vs. Verilog: Clock Generator • VHDL: signal clk : std_logic := ‘0’; process begin clk <= not (clk) after clkperiod/2; wait on clk; end; • Verilog: initial clk = 0; always #(clkperiod/2) clk = ~ clk;

31. Verilog Weakness • Not well suited for complex, high level modeling • No user defined type definition • No concept of libraries, packages, configurations • No ‘generate’ statement - can’t build parameterizedstructural models • No complex types above a two-dimensional array

32. VHDL vs. Verilog:Managing Large designs • VHDL: • Configuration, generate, generic and package statements all help manage large design structures • Verilog: • There are no statements in Verilog that help manage large designs

33. VHDL vs. Verilog:Procedures and Tasks • VHDL: • allows concurrent procedure calls • Verilog: • does not allow concurrent task calls

34. VHDL vs. Verilog:Structural Replication • VHDL: • The generate statement replicates a number of instances of the same design-unit or some sub part of a design, and connects it appropriately • Verilog: • There is no equivalent to the generate statement in Verilog.

35. Languages “under development” • SystemVerilog • Extending Verilog to higher levels of abstraction for architectural and algorithm design and advanced verification • VHDL 200x • Goal of VHDL Analysis and Standards Group (VASG): • Enhance/update VHDL for to improve performance, modeling capability, ease of use, simulation control, and the type system • e.g.: Data types and abstractions: • variant records • interfaces

36. Az összetettség csökkentésének módszerei • Language abstractions use the language to describe complex matters without having to describe small details • Functions and procedures are important parts of the language in order to handle complexity • Design hierarchy uses components in order to conceal details - the black box principle • The term black box means that only inputs/outputs of a component are visible at a certain level • It is the designer who decides how many different hierarchies there are to be in the design

37. Fő sajátságok • VHDL uses the concept of delta delay to keep track of processes that should occur at a given time step, but are actually evaluated in different machine cycles • A delta delay is a unit of time as far as the simulator hardware is concerned, but in the simulation itself time has no advance

38. VHDL összetevők • Components are a central concept in VHDL • Components are used, among other things, to build up component libraries, e.g.: • microprocessors • special user circuits • other standard circuits • If a “good” component has been designed, it can be saved in a component library, enabling it to be copied as many times as required, i.e. components are reusable • this is called creating instances, i.e. creating the component in a schematic or in the text file

39. Objektum alapú nyelv • Staying with computer science a while longer, VHDL is an object-based language, i.e. what separates VHDL from object-oriented languages is that the language does not have inheritance • Generic components and instantiation are typical for object-based languages • Generic components are components which can be modified before instantiation, e.g. a generic component which copes with different width for the input and output signals

40. Feketedoboz használata • The internal structure can be concealed from the designer - the black box principle • In some cases there is no need to know how to component is structured • The designer is usually only interested in • inputs and outputs • a specification function and • access times • The majority of hardware designers are used to working with black boxes such as the 74LSXX circuit family, for example

41. Fő nyelvi szerkezetek Tervezési egyed It is the basic unit of hardware description = egyed bejelentés + építmény Egyed bejelentés:fekete doboz modell Építmény:It describes the relationship between the design entity inputs and outputs Each architecture consists of concurrent statements denoted by CS

42. Concurrent statements define interconnected processes and blocks that together describe a design’s overall behavior or structure They can be grouped using block statement. Groups of blocks can also be partitioned into other blocks At this same level, a VHDL component (CP) can be connected to define signals within the blocks It is a reference to an entity A process can be a single signal assignment statement or a series of sequential statements (SS) Within a process, procedures and functions can partition the sequential statements Egyidejű és sorrendi utasítások

43. Tervezési egyed Egyed bejelentés Építmény Elsődleges nyelvi elvonatkoztatás The primary abstraction level of a VHDL hardware model is the Design Entity. The Design Entity can represent a cell, chip, board, or subsystem A Design Entity is composed of two main parts: 1) An Entity Declaration 2) An Architecture

44. An Entity Declaration defines the interface between the Design Entity and the environment outside of the Design Entity An Architecture describes the relationships between the Design Entity inputs and outputs Elsődleges nyelvi elvonatkoztatás (folyt.)

45. Példa az egyedbejelentésre és az építményre ENTITY and2 ISPORT (a, b: IN bit; q: OUT bit);END and2;ARCHITECTURE example OFand2IS -- declaration hereBEGIN -- statement hereEND example; The entity name in the Architecture has to be the same as the identifier of the corresponding Entity Declaration

46. Egyedbejelentés és építmény • A component is made up of two main parts: • Entity: Port declaration for inputs and outputs • Architecture: structural of behavioural description • Behaviour is defined as a collective name for functions, operations, behaviour and relations • Behaviour can also be a structural description, i.e. the component consists of other components • The entity can be regarded as a black box with inputs and outputs

47. Példák egyedbejelentésre entityvhdl_component1is port ( a : in std_logic; b : out std_logic); endvhdl_component1; entity vhdl_component2is port( signala_in: in std_logic; -- input signalb_out:out std_logic); -- output end vhdl_component2;

48. Egy építmény példakódja architecturevhdl_codeofvhdl_component1is begin B <= not A; .... endvhdl_code; • Two names are specified in the declaration of the architecture: the component name which describes which entity the architecture belongs to, and vhdl_code, which is the name of the architecture

49. Az egyedbejelentés jelölésmódja entity <identifier_name> is port( [signal] <identifier>:[<mode>] <type_indication>; ... [signal] <identifier>:[<mode>] <type_indication>); end [entity] [<identifier_name>]; • The word “entity” in the last line is not supported before the VHDL-93 standard

50. A kapcsok üzemmódjai <mode> = in, out, inout, buffer, linkage in: Component only read the signal out: Component only write to the signal inout: Component read or write to the signal (bidirectional signals) buffer: Component write and read back the signal (no bidirectional signals, the signal is going out from the component) linkage: Used only in the documentation