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Flip-flop Selection to Maximize TDF Coverage with Partial Enhanced Scan

Flip-flop Selection to Maximize TDF Coverage with Partial Enhanced Scan. Gefu Xu Adit D. Singh Auburn University, USA. 2007 IEEE 16th Asian Test Symposium. Outline. Introduction Overview of Enhanced Scan designs Dual Enhanced Scan Flip-flop & Enhanced DTSFF (Delay Test Scan Flip-flop)

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Flip-flop Selection to Maximize TDF Coverage with Partial Enhanced Scan

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  1. Flip-flop Selection to Maximize TDF Coverage with Partial Enhanced Scan Gefu Xu Adit D. Singh Auburn University, USA 2007 IEEE 16th Asian Test Symposium

  2. Outline Introduction Overview of Enhanced Scan designs Dual Enhanced Scan Flip-flop & Enhanced DTSFF (Delay Test Scan Flip-flop) Partial Enhanced Scan Design The Structure of Partial Enhanced Scan Design Scan-unit Selection for Partial Enhanced Scan TDF coverage of Partial Enhanced Scan Refining Scan-unit Selection Interchange Procedure Conclusion

  3. Enhanced Scan Designs 1) Classical Enhanced Scan with alternating regular and scan FFs 2) Enhanced Scan with hold latches

  4. Enhanced Scan FFs with Slow Scan Enable Signals 1)Dual Enhanced Scan Flip-flop [1] 2)Enhanced DTSFF (Delay Test Scan Flip-flop) [1] N. Devtaprasanna, A. Gunda, P. Krishnamurthy, S. M. Reddy and I. Pomeranz, "Methods For Improving Transition Delay Fault Coverage Using Broadside Tests", in Proc.International Test Conference, 2005, pp. 256-265.

  5. Partial Enhanced Scan Design

  6. Example Circuit with Each Node Labeled with The Probability of Logic ‘0’

  7. Ideally desired relationship between Partial Enhanced Scan FF percentage and Fault coverage

  8. Experiment Procedure • Calculate the P(0) of the input of each flip-flop insides the circuit using Controllability Analysis Method • Ordering the flip-flops with respect to their P(0) • Most “biased” flip-flops will be replaced with Enhanced Scan FF first • Running ATPG using Synopsis TetraMax

  9. Results (s13207)

  10. Results (s9234)

  11. Results (s5378) 2 1

  12. Results (s1423) 2 1

  13. Results (s15850) 4 3 2 1

  14. Interchange Procedure Calculate FCN (N=0, 1, 2…20); Interchange_times=0; Delta_Slope_allowable_value= -0.03; Interchange_allowable_times= 30; While (minimum {Delta_SlopeN} < Delta_Slope_allowable_value) && (Interchange_times < Interchange_allowable_times) { Find M, where Delta_SlopeM = minimum {Delta_SlopeN}; Exchange Flip-flops in group GM with flip-flops in group GM-1; Update FCM-1; Interchange_times = Interchange_times +1; }

  15. Results (s5378)

  16. Results (s1423)

  17. Results (s15850)

  18. Conclusion • Partial Enhanced Scan design achieves high TDF coverage & reduces DFT cost • Both Dual Enhanced Scan Flip-flop and Enhanced DTSFF support Enhanced Scan with slow enable signals • Controllability Analysis is used for scan unit selection (prescreening) • Interchange Procedure further refines scan-unit selection

  19. Questions?

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