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Lecture 13 VHDL Structural Modeling

Lecture 13 VHDL Structural Modeling. Hai Zhou ECE 303 Advanced Digital Design Spring 2002. Outline. Structural VHDL Use of hierarchy Component instantiation statements Concurrent statements Test Benches READING: Dewey 12.1, 12.2, 12.3, 12.4, 13.1, 13.2, 13.3. 13.4, 13.6, 13.7. 13.8.

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Lecture 13 VHDL Structural Modeling

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  1. Lecture 13 VHDL Structural Modeling Hai Zhou ECE 303 Advanced Digital Design Spring 2002 ECE C03 Lecture 13

  2. Outline • Structural VHDL • Use of hierarchy • Component instantiation statements • Concurrent statements • Test Benches • READING: Dewey 12.1, 12.2, 12.3, 12.4, 13.1, 13.2, 13.3. 13.4, 13.6, 13.7. 13.8 ECE C03 Lecture 13

  3. A general VHDL design Entity … is … End entity; I1 O1 I2 IO1 s1 component concurrent assignment I1 O1 architecture … of … is ... begin … end; s2 s3 s8 s9 s4 s6 process 1 process 2 concurrent assignment I2 IO1 s5 s7 ECE C03 Lecture 13

  4. Structural Descriptions • A structural description of a system is expressed in terms of subsystems interconnected by signals • Each subsystem may be another design (component) or a process • Component instantiation and port maps entity entity_name (architecture_identifier) port map ( port_name => signal_name expression open, ); ECE C03 Lecture 13

  5. Example of Component Instantiation entity DRAM_controller is port (rd, wr, mem: in bit; ras, cas, we, ready: out bit); end entity DRAM_controller; • We can then perform a component instantiation as follows assuming that there is a corresponding architecture called “fpld” for the entity. main_mem_cont : entity work.DRAM_controller(fpld) port map(rd=>cpu_rd, wr=>cpu_wr, mem=>cpu_mem, ready=> cpu_rdy, ras=>mem_ras, cas=>mem_cas, we=>mem_we); ECE C03 Lecture 13

  6. Example of a four-bit register • Let us look at a 4-bit register built out of 4 D latches reg4 d0 d1 d2 d2 en clk q0 q2 q3 q4 ECE C03 Lecture 13

  7. Behavioral Description of Register Architecture behavior of reg4 is begin storage : process is variable stored_d0, stored_d1, stored_d2, stored_d3: bit; begin if en = ‘1’ and clk = ‘1’ then stored_d0 := d0; -- variable assignment stored_d1 := d1; stored_d2 := d2; stored_d3 := d3; endif; q0 <= stored_d0 after 5 nsec; q1 <= stored_d1 after 5 nsec; q2 <= stored_d2 after 5 nsec; q3 <= stored_d3 after 5 nsec; wait on d0, d1, d2, d3; end process storage; end architecture behavior; ECE C03 Lecture 13

  8. Structural Composition of Register d_latch d q d0 q0 clk d_latch d d1 q q1 clk d_latch d d2 q q2 clk d_latch d3 d and2 q q3 en a y clk clk b int_clk ECE C03 Lecture 13

  9. Structural VHDL Description of Register entity d_latch is port(d, clk: in bit; q: out bit); end d_latch; architecture basic of d_latch is begin latch_behavior: process is begin if clk = ‘1’ then q <= d after 2 ns; end if; wait on clk, d; end process latch_behavior; end architecture basic; entity and2 is port (a, b: in bit; y: out bit); end and2; architecture basic of and2 is begin and2_behavior: process is begin y <= a and b after 2 ns; wait on a, b; end process and2_behavior; end architecture basic; ECE C03 Lecture 13

  10. Structural VHDL Description of Register entity reg4 is port(d0, d1, d2, d3, en, clk: in bit; q0, q1, q2, q3: out bit); end entity reg4; architecture struct of reg4 is signal int_clk : bit; begin bit0: entity work.d_latch(basic) port map(d0, int_clk, q0); bit1: entity work.d_latch(basic) port map(d1, int_clk, q1); bit2: entity work.d_latch(basic) port map(d2, int_clk, q2); bit0: entity work.d_latch(basic) port map(d3, int_clk, q3); gate: entity work.and2(basic) port map(en, clk, int_clk); end architecture struct; ECE C03 Lecture 13

  11. Mixed Structural and Behavioral Models • Models need not be purely structural or behavioral • Often it is useful to specify a model with some parts composed of interconnected component instances and other parts using processes • Use signals as a way to join component instances and processes • A signal can be associated with a port of a component instance and can be assigned to or read in a process ECE C03 Lecture 13

  12. Example of Mixed Modeling: Multiplier architecture mixed of multiplier is signal partial_product, full_product: integer; signal arith_control, result_en, mult_bit, mult_load: bit; begin -- mixed arith_unit: entity work.shift_adder(behavior) port map( addend => multiplicand, augend => full_product, sum => partial_product, add_control => arith_control); result : entity work,reg(behavior) port map (d => partial_product, q => full_product, en => result_en, reset => reset); multiplier_sr: entity work.shift_reg(behavior) port map (d => multiplier, q => mult_bit, load => mult_load, clk => clk); product <= full_product; control_section: process is begin -- sequential statements to assign values to control signals end process control_section; end architecture mixed; Entity multiplier is port(clk, reset: in bit; multiplicand, multiplier: in integer; product: out integer; end entity multiplier; Multiplier (register) multiplicand Arith_unit (shift adder) clk Result (shift register) ECE C03 Lecture 13

  13. Component and Signal Declarations • The declarative part of the architecture STRUCTURE contains: • component declaration • signal declaration • Example of component declaration • component AND2_OP • port (A, B: in bit; Z : out bit); • end component; • Components and design entities are associated by signals, e.g. A_IN, B_IN • Signals are needed to interconnect components • signal INT1, INT2, INT3: bit; ECE C03 Lecture 13

  14. Component Instantiation Statements • The statement part of an architecture body of a structural VHDL description contains component instantiation statements • FORMAT label : component_name port map (positional association of ports); label : component_name port map (named association of ports); • EXAMPLES A1: AND2_OP port map (A_IN, B_IN, INT1); A2: AND2_OP port map (A=>A_IN, C=>C_IN,Z=>INT2); ECE C03 Lecture 13

  15. Hierarchical Structures • Can combine 2 MAJORITY functions (defined earlier) and AND gate to form another function entity MAJORITY_2X3 is port (A1, B1,C1,A2, B2, C2: in BIT; Z_OUT: out BIT); end MAJORITY_2X3; architecture STRUCTURE of MAJORITY_2X3 is component MAJORITY port (A_IN, B_IN, C_IN: in BIT; Z_OUT : out BIT); end component; component AND2_OP port (A, B: in BIT; Z: out BIT); end component; signal INT1, INT2 : BIT; begin M1: MAJORITY port map (A1, B1, C1, INT1); M2: MAJORITY port map (A1, B2, C2, INT2); A1: AND2_OP port map (INT1, INT2, Z_OUT); end STRUCTURE; ECE C03 Lecture 13

  16. Concurrent Signal Assignments entity XOR2_OP is port (A, B: in BIT; Z : out BIT); end entity; -- body architecture AND_OR of XOR2_OP is begin Z <= (not A and B) or (A and not B); end AND_OR; • The signal assignment Z <= .. Implies that the statement is executed whenever an associated signal changes value ECE C03 Lecture 13

  17. Concurrent Signal Assignment entity XOR2_OP is port (A, B: in BIT; Z : out BIT); end entity; -- body architecture AND_OR_CONCURRENT of XOR2_OP is --signal declaration; signal INT1, INT2 : BIT; begin -- different order, same effect INT1 <= A and not B; -- INT1 <= A and not B; INT2 <= not A and B; -- Z <= INT1 or INT2; Z <= INT1 or INT2; -- INT2 <= not A and B; end AND_OR_CONCURRENT; • Above, the first two statements will be executed when A or B changes, and third if Z changes • Order of statements in the text does not matter ECE C03 Lecture 13

  18. Concurrent and Sequential Statements • VHDL provides both concurrent and sequential signal assignment statements • Example SIG_A <= IN_A and IN_B; SIG_B <= IN_A nor IN_C; SIG_C <= not IN_D; • The above sequence of statements can be concurrent or sequential depending on context • If above appears inside an architecture body, it is a concurrent signal assignment • If above appears inside a process statement, they will be executed sequentially ECE C03 Lecture 13

  19. Data Flow Modeling of Combinational Logic • Consider a parity function of 8 inputs entity EVEN_PARITY is port (BVEC : in BIT_VECTOR(7 downto 0); PARITY: out BIT); end EVEN_PARITY; architecture DATA_FLOW of EVEN_PARITY is begin PARITY <= BVEC(0) xor BVEC(1) xor BVEC(2) xor BVEC(3) xor BVEC(4) xor BVEC(5) xor BVEC(6) xor BVEC(7) end DATA_FLOW; ECE C03 Lecture 13

  20. Alternative Logic Implementations of PARITY TREE CONFIGURATION CASCADE CONFIGURATION ECE C03 Lecture 13

  21. Tree Configuration architecture TREE of EVEN_PARITY is signal INT1, INT2, INT3, INT4, INT5, INT6 : BIT; begin INT1 <= BVEC(0) xor BVEC(1) ; INT2 <= BVEC(2) xor BVEC(3) ; INT3 <= BVEC(4) xor BVEC(5) ; INT4 <= BVEC(6) xor BVEC(7); --second row of tree INT5 <= INT1 xor INT6; INT6 <= INT3 xor INT4; -third row of tree PARITY <= INT5 xor INT6; end TREE; ECE C03 Lecture 13

  22. Cascaded Configuration architecture CASCADE of EVEN_PARITY is signal INT1, INT2, INT3, INT4, INT5, INT6 : BIT; begin INT1 <= BVEC(0) xor BVEC(1) ; INT2 <= INT1 xor BVEC(2); INT3 <= INT2 xor BVEC(3) ; INT4 <= INT3 xor BVEC(4); INT5 <= INT4 xor BVEC(5); INT6 <= INT5 xor BVEC(6); PARITY <= INT6 xor BVEC(7); end CASCADE; ECE C03 Lecture 13

  23. Alternative Architecture Bodies • Three different VHDL descriptions of the even parity generator were shown • They have the same interface but three different implementation • Use the same entity description but different architecture bodies architecture DATA_FLOW of EVEN_PARITY is ... architecture TREE of EVEN_PARITY is ... architecture CASCADE of EVEN_PARITY is ... ECE C03 Lecture 13

  24. Test Benches • One needs to test the VHDL model through simulation • We often test a VHDL model using an enclosing model called a test bench • A test bench consists of an architecture body containing an instance of the component to be tested • It also consists of processes that generate sequences of values on signals connected to the component instance ECE C03 Lecture 13

  25. Example Test Bench Entity test_bench is end entity test_bench; architecture test_reg4 of test_bench is signal d0, d1, d2, d3, en, clk, q0, q1, q2, q3: bit; begin dut: entity work.reg4(behav) port map (d0, d1, d2, d3, d4, en, clk, q0, q1, q2, q3); stimulus: process is begin d0 <= ‘1’; d1 <= ‘1’; d2 <= ‘1’; d3 <= ‘1’; en <= ‘0’; clk <= ‘0’; wait for 20 ns; en <= ‘1’; wait for 20 ns; clk <= ‘1’; wait for 20 ns; d0 <= ‘0’; d1 <= ‘0’; d2 <= ‘0’; d3 <= ‘0’; wait for 20 ns; en <= ‘0’; wait for 20 ns; …. wait; end process stimulus; end architecture test_reg4; ECE C03 Lecture 13

  26. Summary • Structural VHDL • Use of Hierarchy • Component instantiation statements • Concurrent statements • Test Benches • READING: Dewey 17.1, 17.3, 17.4, 17.5, 17.6, 17.7, 17.8, 17.10, 18.1, 18.2 ECE C03 Lecture 13

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