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CPRE 583 Reconfigurable Computing Lecture 18: Wed 10/26/2011 (CoreGen Overview) PowerPoint PPT Presentation


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CPRE 583 Reconfigurable Computing Lecture 18: Wed 10/26/2011 (CoreGen Overview). Instructor: Dr. Phillip Jones ([email protected]) Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA. http://class.ece.iastate.edu/cpre583/. Announcements/Reminders. MP3: Due 11/4

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CPRE 583 Reconfigurable Computing Lecture 18: Wed 10/26/2011 (CoreGen Overview)

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Cpre 583 reconfigurable computing lecture 18 wed 10 26 2011 coregen overview

CPRE 583Reconfigurable ComputingLecture 18: Wed 10/26/2011(CoreGen Overview)

Instructor: Dr. Phillip Jones

([email protected])

Reconfigurable Computing Laboratory

Iowa State University

Ames, Iowa, USA

http://class.ece.iastate.edu/cpre583/


Announcements reminders

Announcements/Reminders

  • MP3: Due 11/4

    • IT should have resolved the issue that was causing problems running MP3 on some of the linux-X and research-X remote machines

  • Weekly Project Updates due: Friday’s (midnight)

  • Will post ML507 ucf for quick reference


Project grading breakdown

Project Grading Breakdown

  • 50% Final Project Demo

  • 30% Final Project Report

    • 20% of your project report grade will come from your 5-6 project updates. Friday’s midnight

  • 20% Final Project Presentation


Projects ideas relevant conferences

Projects Ideas: Relevant conferences

  • Micro

  • Super Computing

  • HPCA

  • IPDPS

  • FPL

  • FPT

  • FCCM

  • FPGA

  • DAC

  • ICCAD

  • Reconfig

  • RTSS

  • RTAS

  • ISCA


Projects target timeline

Projects: Target Timeline

  • Teams Formed and Topic: Mon 10/10

    • Project idea in Power Point 3-5 slides

      • Motivation (why is this interesting, useful)

      • What will be the end result

      • High-level picture of final product

    • Project team list: Name, Responsibility

  • High-level Plan/Proposal: Fri 10/14

    • Power Point 5-10 slides (presentation to class Wed 10/19)

      • System block diagrams

      • High-level algorithms (if any)

      • Concerns

        • Implementation

        • Conceptual

      • Related research papers (if any)


Projects target timeline1

Projects: Target Timeline

  • Work on projects: 10/19 - 12/9

    • Weekly update reports

      • More information on updates will be given

  • Presentations: Finals week

    • Present / Demo what is done at this point

    • 15-20 minutes (depends on number of projects)

  • Final write up and Software/Hardware turned in: Day of final (TBD)


Initial project proposal slides 5 10 slides

Initial Project Proposal Slides (5-10 slides)

  • Project team list: Name, Responsibility (who is project leader)

    • Team size: 3-4 (5 case-by-case)

  • Project idea

    • Motivation (why is this interesting, useful)

    • What will be the end result

    • High-level picture of final product

  • High-level Plan

    • Break project into mile stones

      • Provide initial schedule: I would initially schedule aggressively to have project complete by Thanksgiving. Issues will pop up to cause the schedule to slip.

    • System block diagrams

    • High-level algorithms (if any)

    • Concerns

      • Implementation

      • Conceptual

  • Research papers related to you project idea


  • Weekly project updates

    Weekly Project Updates

    • The current state of your project write up

      • Even in the early stages of the project you should be able to write a rough draft of the Introduction and Motivation section

    • The current state of your Final Presentation

      • Your Initial Project proposal presentation (Due Wed 10/19). Should make for a starting point for you Final presentation

    • What things are work & not working

    • What roadblocks are you running into


    Common questions

    Common Questions


    Common questions1

    Common Questions


    Coregen

    CoreGen

    • A tool for generating/customizing components made available from Xilinx.

    • A wide range of component families available

      • Basic FPGA components (Block RAM, multipliers)

      • More advanced components (Clock Managers)

      • Math cores

      • Communication protocol cores

      • Signal processing cores


    Coregen1

    CoreGen

    • BlockRAM

    • DCM (Digital Clock Manger)


    Coregen2

    CoreGen

    • BlockRAM

      • 18/36-Kbit size memory block distributed throughout the FPGA

      • Can be combined to create lager effective memory blocks

      • Important: See data sheet for the amount of memory resources available on a give FPGA

    • DCM (Digital Clock Manger)


    Coregen block ram

    CoreGen (Block RAM)

    FPGA

    LUT

    Block

    RAM


    Coregen block ram1

    CoreGen (Block RAM)

    Block RAM

    (36-Kbit)

    Address 1023

    10-bit

    Address_A

    36-bit

    Data_in_A

    36-bit

    Data_out_A

    Address 0

    36-bit


    Coregen block ram2

    CoreGen (Block RAM)

    Block RAM

    (36-Kbit)

    Address 4096

    12-bit

    Address_A

    36-bit

    Data_in_A

    36-bit

    Data_out_A

    Address 0

    9-bit

    Can configure to change size of each word


    Coregen block ram3

    CoreGen (Block RAM)

    Block RAM

    (36-Kbit)

    Block RAM

    (36-Kbit)

    Address 1023

    Address 1023

    10-bit

    Address_A

    72-bit

    Data_in_A

    72-bit

    Data_out_A

    Address 0

    Address 0

    72-bit

    Can configure to change size of each word


    Coregen block ram4

    CoreGen (Block RAM)

    Block RAM

    (36-Kbit)

    Address 1023

    10-bit

    10-bit

    Address_A

    Address_B

    36-bit

    36-bit

    Data_in_A

    Data_in_B

    36-bit

    36-bit

    Data_out_A

    Data_out_B

    Address 0

    36-bit

    Can be 2-ported (dual-ported)


    Coregen block ram5

    CoreGen (Block RAM)

    • Declare and Instantiate a core generated by coregen like any other component

    • Example: RAM_1K_36bit

    -- Declare

    -- Instantiate


    Coregen block ram6

    CoreGen (Block RAM)


    Coregen block ram7

    CoreGen (Block RAM)


    Coregen block ram8

    CoreGen (Block RAM)

    • Target the 70FX FPGA (what we use for class)


    Coregen block ram9

    CoreGen (Block RAM)

    • Select type of core you want to build. In this case a RAM block

    Double-click


    Coregen block ram10

    CoreGen (Block RAM)

    • Set parameters

    Name


    Coregen block ram11

    CoreGen (Block RAM)

    • Set parameters

    Set size


    Coregen block ram12

    CoreGen (Block RAM)


    Coregen block ram13

    CoreGen (Block RAM)

    Check Resources used

    Generate Core


    Coregen3

    CoreGen

    • BlockRAM

    • DCM (Digital Clock Manger)

      • Takes an input clock an multiplies by a factor (M/D)

        • M is the multiplier

        • D is the divider

      • Can generate multiple clock

      • Can set phase relation between clock

      • Can be change dynamically at run-time (Advanced usage)

      • Also a Phase Locked-Loop version of the DCM exists


    Coregen dcm

    CoreGen (DCM)

    FPGA

    LUT

    Block

    RAM

    DCM


    Coregen block ram14

    CoreGen (Block RAM)

    DCM

    M=?

    D=?

    CLK_out_1x

    CLK_in

    CLK_out_2x

    CLK_out_1x_180deg

    CLK_out_FX

    Lock

    FX = M/D

    e.g. M= 8, D=2: then

    FX = 8/2 = 4

    Lock: Indicates when the output

    Clock of the DCM are stable and

    Read for use.

    reset <= reset_extern OR not(Lock)


    Next class

    Next Class

    • Design Patterns and Compute Models

      • Chapter 5.1, Reading 7


    Questions comments concerns

    Questions/Comments/Concerns

    • Write down

      • Main point of lecture

      • One thing that’s still not quite clear

      • If everything is clear, then give an example of how to apply something from lecture

    OR


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