Design and Implementation of VLSI Systems (EN1600) Lecture 16: Interconnects &amp; Wire Engineering

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Design and Implementation of VLSI Systems (EN1600) Lecture 16: Interconnects &amp; Wire Engineering. Prof. Sherief Reda Division of Engineering, Brown University Spring 2008. [sources: Weste/Addison Wesley – Rabaey/Pearson]. A capacitor does not like to change its voltage instantaneously.

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Design and Implementation of VLSI Systems

(EN1600)

Lecture 16: Interconnects & Wire Engineering

Prof. Sherief Reda

Division of Engineering, Brown University

Spring 2008

A capacitor does not like to change its voltage instantaneously.

A wire has high capacitance to its neighbor.

When the neighbor switches from 1→ 0 or 0 →1, the wire tends to switch too.

Called capacitive coupling or crosstalk.

Crosstalk has two harmful effects:

Increased delay on switching wires

Noise on nonswitching wires

Interconnects introduce cross talk
Assume layers above and below on average are quiet

Second terminal of capacitor can be ignored

Model as Cgnd = Ctop + Cbot

Effective Cadj depends on behavior of neighbors

Miller effect

1. Crosstalk impacts delay
Crosstalk causes noise on nonswitching wires

If victim is floating:

model as capacitive voltage divider

2.Crosstalk also creates noise
Usually victim is driven by a gate that fights noise

Noise depends on relative resistances

Victim driver is in linear region, agg. in saturation

If sizes are same, aggressor = 2-4 x Rvictim

Crosstalk noise effects

(time constant depends on the ratio of time constant of aggressor and victim)

Simulating noise induced by coupling
• Noise is less than the noise margin → nothing happens
• Static CMOS logic will eventually settle to correct output even if disturbed by large noise spikes
• But glitches cause extra delay and power
• Large driver oppose the coupling sooner → smaller noise
• Memories are more sensitive
Goal: achieve delay, area, power goals with acceptable noise

Possible solutions:

1. Width, Spacing, Layer

2. Shielding

3. Repeater insertion

4. Wire staggering and differential signaling

Wire Engineering
1/2. Width, Spacing, Layer, Shielding
• Widening a wire reduces resistance but increases capacitance (but less proportionally) → RC delay product improves
• Spacing reduces capacitance → improves RC delay
• Layers
• Coupling can be avoided if adjacent lines do not switch → shield critical nets with power or ground wires on one or both sides to eliminate coupling
R and C are proportional to l

RC delay is proportional to l2

Unacceptably great for long wires

Break long wires into N shorter segments

Drive each one with a repeater or buffer

buffer/repeater

3. Repeater insertion

source

sink

• Two questions:
• What is the position that minimizes the delay?
• How many repeaters to insert to minimize the delay?

source

L

sink

x

buffer

Minimum delay is attained when

Makes sense to add a buffer only if D0-D1 > 0

A. If there are multiple buffers, where are the optimal locations to insert them?

source

L

sink

L/2

L/2

If Rbuf = Rsnk and Csnk = Cbuf

then the optimal location for the buffer is at distance L/2

If there are N buffers then minimum delay will occur when they are equally spaced, i.e., separation distance is L/(N+1)

4. Staggering and differential signaling

staggering

differential signaling