Design and Implementation of VLSI Systems (EN1600) Lecture 16: Interconnects & Wire Engineering. Prof. Sherief Reda Division of Engineering, Brown University Spring 2008. [sources: Weste/Addison Wesley – Rabaey/Pearson]. A capacitor does not like to change its voltage instantaneously.
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Design and Implementation of VLSI Systems
Lecture 16: Interconnects & Wire Engineering
Prof. Sherief Reda
Division of Engineering, Brown University
[sources: Weste/Addison Wesley – Rabaey/Pearson]
A capacitor does not like to change its voltage instantaneously.
A wire has high capacitance to its neighbor.
When the neighbor switches from 1→ 0 or 0 →1, the wire tends to switch too.
Called capacitive coupling or crosstalk.
Crosstalk has two harmful effects:
Increased delay on switching wires
Noise on nonswitching wires
Assume layers above and below on average are quiet
Second terminal of capacitor can be ignored
Model as Cgnd = Ctop + Cbot
Effective Cadj depends on behavior of neighbors
Crosstalk causes noise on nonswitching wires
If victim is floating:
model as capacitive voltage divider
Usually victim is driven by a gate that fights noise
Noise depends on relative resistances
Victim driver is in linear region, agg. in saturation
If sizes are same, aggressor = 2-4 x Rvictim
(time constant depends on the ratio of time constant of aggressor and victim)
Goal: achieve delay, area, power goals with acceptable noise
1. Width, Spacing, Layer
3. Repeater insertion
4. Wire staggering and differential signaling
R and C are proportional to l
RC delay is proportional to l2
Unacceptably great for long wires
Break long wires into N shorter segments
Drive each one with a repeater or buffer
Minimum delay is attained when
Makes sense to add a buffer only if D0-D1 > 0
If Rbuf = Rsnk and Csnk = Cbuf
then the optimal location for the buffer is at distance L/2
If there are N buffers then minimum delay will occur when they are equally spaced, i.e., separation distance is L/(N+1)