1 / 5

BCD adder

BCD adder. 4-Bit adder. 4-Bit adder. VHDL code for BCD adder. entity BCDadder is Port ( bcd1 : in std_logic_vector(3 downto 0); bcd2 : in std_logic_vector(3 downto 0); bcdcarryin : in std_logic; bcdsum : out std_logic_vector(3 downto 0);

aderes
Download Presentation

BCD adder

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. BCD adder DSD,USIT,GGSIPU

  2. 4-Bit adder 4-Bit adder DSD,USIT,GGSIPU

  3. VHDL code for BCD adder • entity BCDadder is • Port ( bcd1 : in std_logic_vector(3 downto 0); • bcd2 : in std_logic_vector(3 downto 0); • bcdcarryin : in std_logic; • bcdsum : out std_logic_vector(3 downto 0); • bcdcarryout : out std_logic); • end BCDadder; DSD,USIT,GGSIPU

  4. architecture Behavioral of BCDadder is • component adder4bit is • Port ( a : in std_logic_vector(3 downto 0); • b : in std_logic_vector(3 downto 0); • carryin : in std_logic; • sum : out std_logic_vector(3 downto 0); • carryout : out std_logic); • end component adder4bit; • signal s,x: std_logic_vector(3 Downto 0); • signal c,K : std_logic; • begin • u1:adder4bit port map(a(3)=>bcd1(3),a(2)=>bcd1(2),a(1)=>bcd1(1),a(0)=>bcd1(0), • b(3)=>bcd2(3),b(2)=>bcd2(2),b(1)=>bcd2(1),b(0)=>bcd2(0), • carryin=>bcdcarryin,sum(3)=>s(3),sum(2)=>s(2),sum(1)=>s(1),sum(0)=>s(0),carryout=>c); • K <= (s(3)and s(2))or(s(3)and s(1))or(c); • x <= "0110" when k ='1' else • "0000"; • u2 :adder4bit port map(a(3)=>s(3),a(2)=>s(2),a(1)=>s(1),a(0)=>s(0),b(3)=>x(3),b(2)=>x(2),b(1)=>x(1),b(0)=>x(0),carryin=>'0', • sum(3)=>bcdsum(3),sum(2)=>bcdsum(2),sum(1)=>bcdsum(1),sum(0)=>bcdsum(0), • carryout=>bcdcarryout); • end Behavioral; DSD,USIT,GGSIPU

  5. Waveform of bcd adder DSD,USIT,GGSIPU

More Related