Power-Performance simulation and analysis of Conventional and Speculative TLP

1. Power-Performance simulation and analysis of Conventional and Speculative TLP Project Presentation Ashok Venkatesan, 1200858585 CSE 520

2. Motivation • Paper had been presented on a unified architecture for conventional and speculative multithreading. • Ample scope for investigating on the power consumption patterns of speculative threading. • With a huge emphasis on lowering power consumption in CMPs, this project can be of good value in helping identify improvements that can be made to such architectures.

3. Implementation • Simplescalar 2.0 • Machine Endianness Issues • A new simulator coded in C • Functional Simulator • Simple Code • Supports multi-threading • Supports an ISA containing common commands which include logical, arithmetic and branching operations. • Has a new command called Fork • Scalable number of cores

4. Micro-benchmarks LD R1 512 LD R2 520 FORK JMP TLOOP LABEL TEND STOP JMP CONT LABEL TLOOP CMP R1 0 JNL TEND ADD R2 5 SUB R1 1 JMP TLOOP LABEL CONT SW R2 520 LD R3 530 LD R1 513 LABEL LP2 CMP R1 0 JNL LP2END LDR R3 R2 ADD R2 1 SWR R2 R3 SUB R1 1 JMP LP2 LABEL LP2END END LD R1 512 LD R2 520 LABEL LOOP CMP R1 0 JNL LEND ADD R2 5 SUB R1 1 JMP LOOP LABEL LEND SW R2 520 LD R3 530 LD R1 513 LABEL LP2 CMP R1 0 JNL LP2END LDR R3 R2 ADD R2 1 SWR R2 R3 SUB R1 1 JMP LP2 LABEL LP2END END a)‏ c)‏ b)‏

5. Results Total clock cycles = 12347 Total instruction count = 6164 Instructions per Cycle = 0.50 CPU #1 Utilization = 100.00% CPU #1 L1 Hits = 3587 CPU #2 Utilization = 66.41% CPU #2 L1 Hits = 2557 Total L1 Cache Hits = 6144 Total L1 Cache Misses = 536 L1 Cache Hit Ratio = 0.92 Memory Idle Percent = 99.68% a)‏ Total clock cycles = 20544 Total instruction count = 6162 Instructions per Cycle = 0.30 CPU #1 Utilization = 100.00% CPU #1 L1 Hits = 6143 CPU #2 Utilization = 0.00% CPU #2 L1 Hits = 0 Total L1 Cache Hits = 6143 Total L1 Cache Misses = 534 L1 Cache Hit Ratio = 0.92 Memory Idle Percent = 99.69% c)‏ b)‏

6. Thank you