1 / 16

A New Online BIST Method for NoC Interconnects

A New Online BIST Method for NoC Interconnects. Elnaz Koopahi Zainalabedin Navabi. School of Electrical and Computer Engineering University of Tehran, Tehran, Iran. {koopahi, navabi}@cad.ut.ac.ir. Outline. Introduction Online Testing NoC Platform NoC Architecture

adanna
Download Presentation

A New Online BIST Method for NoC Interconnects

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. A New Online BIST Method for NoC Interconnects Elnaz Koopahi Zainalabedin Navabi School of Electrical and Computer Engineering University of Tehran, Tehran, Iran {koopahi, navabi}@cad.ut.ac.ir Elnaz Koopahi University of Tehran

  2. Outline • Introduction • Online Testing • NoC Platform • NoC Architecture • Verilog HDL Test Platform • The Proposed Test Method • Using Spare Times • BIST Hardware • Test Mode Operation • Test Pattern Generation • Experimental Results • Conclusions Elnaz Koopahi University of Tehran

  3. Introduction • NoC as a new design paradigm to replace traditional SoC • A typical NoC: Switches, Links, Cores, Network Interfaces • Providing appropriate test mechanisms to ensure the demanded reliability • Consider the circuit properties to implement an acceptable test method Elnaz Koopahi University of Tehran

  4. Introduction (cont.) • Regular versus custom-built irregular structures Regular has: • Predictable electrical parameters • Long Latency and poor link usage • I/O limitation • Poor controllability and observability • Selecting Built-in-self test (BIST) as a solution Elnaz Koopahi University of Tehran

  5. Online Testing • Faults: • Permanent • Intermittent • Transient • Important parameters: • Error coverage • Error latency • Space redundancy • Time redundancy • Not Concurrent (does not use actual data), but Online simultaneous with normal operation of NoC Elnaz Koopahi University of Tehran

  6. NoC Architecture • Regular 2-D NoC Architecture • Packet switched • XY routing algorithm Elnaz Koopahi University of Tehran

  7. Verilog HDL Test Platform • Verilog-based test platform features • Fault injection • Fault simulation • Support for the test method • Add the BIST hardware Elnaz Koopahi University of Tehran

  8. Using Spare Times • Regular NoC: Long Latency and poor link usage • Sending test packets in spare times Elnaz Koopahi University of Tehran

  9. Using Spare Times (cont.) • Calculating the test time • Providing the required spare time during the design and application mapping • Interlacing the test process • multiple test sessions Elnaz Koopahi University of Tehran

  10. BIST Hardware • Using PUT signal for detecting incoming packet • Test Hardware for test data generation • Test Hardware for response analyses Elnaz Koopahi University of Tehran

  11. Test Mode Operation //In every clock cycle //State machine for receiving the packet from router and sending the flits to output port CASE (cur_out_state) IS GetPacket: if(~Put) Data_out<= Test Data; Else //do normal tasks ... END CASE; //State machine for receiving the packet from adjacent switch CASE (cur_in_state) IS GetStartByte: if (Data_In == FAULT_DETECTED) out_port is faulty else if ( (Data_In != SB) && (Data_In != Testdata)) in_port is faulty Elnaz Koopahi University of Tehran

  12. Test Pattern Generation All Faults Stuck-at Faults • Stuck-at fault models • Wired-OR and wired-AND fault models • Delay faults • Inverted true/complement algorithm, ITCC Elnaz Koopahi University of Tehran

  13. Experimental Results • No need for extra time for performing online testing • NI Hardware overhead: • Approximately 3.05% for stuck-at faults • Approximately 3.2% for stuck-at and bridging faults • Requires: 2 free clock cycles to detect stuck-at faults • Requires: 2*LogN free clock cycle for supporting delay and bridging faults Elnaz Koopahi University of Tehran

  14. Using Spare Times, Switch Testing • Switch testing • BIST gets involved when switch is not routing Test while not routing Elnaz Koopahi University of Tehran

  15. Conclusions • Verilog HDL NoC platform • Online BIST method: • Full fault coverage for interconnect faults • No time redundancy • Negligible hardware overhead added to switches • A new constraint in design and application mapping • Can be expanded to test router and FIFOs Elnaz Koopahi University of Tehran

  16. Thanks Elnaz Koopahi University of Tehran

More Related