MEMS Technologies—Surface Micromachining

1. MEMS Technologies—Surface Micromachining mems tech surf.ppt 19 Mar 2007

2. Surface Micromachining Surface micromachining is a MEMS technology that uses the same thin film fabrication processes as are used in microelectronics fabrication. A main characteristic of surface micromachining is the deposition of alternatinglayers of structural materials (Si for example) and sacrificial materials (an oxide layer for example). After the stack is completed, using deposition and photolithographic patterning to construct a 3-dimensional structure, the final step is a releaseetch. In the release etch, all the sacrificial materials are removed, leaving the completed mechanical structure capable of motion. In this way, surface micromachining is a planar fabrication technology just like microelectronic fabrication. Polycrystallinesilicon (polysilicon or just poly) is a standard structural material and SiO2 is a standard sacrificial material. The release etch in this case could be a mixture using hydrofluoric acid (HF).

3. Standard Device Fabrication Sequence Recall the primary processes that are used in microelectronics include film deposition photolithography to make a patterned mask on the film etch of the film (pattern transfer) by wet or dry etch methods other processes (e.g. doping, anneals, etc…) repeat the sequence… photolithography film deposition etch other processes Note that even though surface micromachining uses the same methods as microelectronic fabrication, these MEMS devices are usually much larger (~100 µm) and thicker (few µm) than microelectronic devices (usually < 1 µm and << 1 µm).

4. Patterning using Photolithography & Pattern Transfer by Etching All the patterns (devices features) to make the transistors are made using the photolithographic process. 8. Selectively process the substrate in the opening. 7. Strip the remaining photoresist. 6. Etch film using resist as a mask. 3. Align photomask to wafer features. 5. Develop photoresist. 4. Expose photoresist through mask. 1. Spin photoresist onto wafer. 2. Softbake photoresist to dry it.

5. Surface Micromachined Cantilever Construction of a cantilever beam by surface micromachining. isolation layer Si substrate Patterning of isolation layer to assure a complete release etch. Conformal deposition of sacrificial layer followed by etch of hole for cantilever attachment. Conformal deposition of cantilever material. Release etch of sacrificial material to release the cantilever. Fabricated cantilever.

6. Surface Micromachined Cantilever—Fabrication Scheme Layout

7. CMP as an Enabler for Surface Micromachining One fabrication method that has enabled surface micromachining, particular multi-level MEMS devices, was developed for advanced multi-level microelectronic ICs. This method is called chemicalmechanical planarization (or polishing), usually known as CMP. As microelectronic devices are made smaller and in higher densities, individual transistors are closer-spaced. As the thin films are deposited to make them, the surface of the wafer becomes progressively more bumpy due to the topography of the devices. This increase in surface topography makes high resolution photolithography (needed to pattern ever-smaller device features) more difficult. The reason is its small depth-of-focus (DOF), required for the high resolution (small features). As more layers of interconnecting wires are needed for high density ICs, the DOF problem makes photolithography problematic.

8. High Density Devices—Topography Issues

10. Photolithography & Tall Features on a Wafer The solution: deposit more ILD than needed, then polish the surface to make it flat.

11. Chemical Mechanical Polishing (CMP) Polish the bumpy surface using a slurry of silica particles (SiO2) and alkaline chemicals (like KOH) on a polishing pad. After polishing, the surface is flat and makes subsequent photolithography on top of it much easier.

13. Surface topography due to conventional LOCOS Original IBM Cu Damascene process 5-level metal process, 120 nm, STMicrotech

15. Surface Micromachining Technologies A variety of surface micromachining technologies exist. Each uses different structural / sacrificial materials choices with different capabilities. Some have demonstrated commercial products (TI DMD) The precise selection of materials, both structural & sacrificial, depends upon the application. It also depends upon the entirety of properties of the candidate material including mechanical properties (stress, Young’s modulus, hardness), thermal budgets, available material processing capabilities, etc…

16. Typical MEMS Devices by Surface Micromachining electrostatic micromotor (MEMS Exchange) cantilevers (Ga Tech) structural material: poly Si sacrificial material: SiO2 chain microgear (Sandia)

17. Texas Instruments Deformable Mirror Device (DMD) One of the most well-known surface micromachined devices is the TI DMD, used for high definition displays. TI calls its technology digital light processing or DLP. The packaged DMD chip is ~ 2” on a side and contains ~ 1.3 million individually-addressable moving Al mirrors behind a transparent window. individual Al mirrors How the display technology works.

18. TI DMD Design Layout by Layers assembled DMD layers mirror layer base layer SEM views of the DMD individual DMD layers yoke layer

19. Sandia SUMMiT V Process—Surface Micromachining The Sandia SUMMiT V Process uses a specific set of fabrication processes to make MEMS devices by surface micromachining. The structural material is poly silicon deposited by LPCVD. The sacrificial material is SiO2, also deposited by LPCVD. Other parts of the process sequence include plasma etches (RIE) for small parts of the devices and a wet etch for certain parts (hubs). The final release step is a wet etch using HF acid. optical switch (Sandia) ratcheted microgear (Sandia)

20. SUMMiT V Process Layers Sandia ultraplanar multilevel MEMS technology (SUMMiT V) uses 5 levels of poly Si and sacrificial oxide layers & 14 photolithography steps. At the end, it has 1 ground plane and 1 electrical layer with 4 mechanical layers. Devices up to 12 µm high with large stiffness and robustness can be made.

21. SUMMiT V Process Sequence red = structural poly green = sac oxide blue = mask layer • 0. Start with a clean n-type Si 100 wafer • Grow thermal oxide SiO2 ~ 0.63 µm for electrical insulation. • Deposit low stress nitride SiNx ~ 0.8 µm to act as etch stop. Pattern/etch with nitride_cut mask for electrical contacts to substrate. • Deposit 0.3 µm doped poly Si (poly0), pattern/etch with mmpoly0 mask, for either mechanical anchor, ground or wiring layer. • Deposit 1st sacrificial oxide layer (sacox1), 2 µm in conformal layer on mmpoly0 layer; pattern/etch with dimple_cut mask to form dimples (dimple depth controlled using timed etch 1.5 µm deep. • Pattern sacox1 layer a 2nd time with sacox1_cut mask to form anchor sites to the mmpoly0 layer. • Deposit 1 µm of doped poly Si conformally (poly1), pattern/etch with mmpoly1 mask to define a structure in the layer or with pin_joint_cut to define a hub for a rotating member. • Deposit 0.3 µm of oxide (sacox2); pattern/etch with sacox2. Can use this oxide as a hard mask for mmpoly1. • Deposit 1.5 µm of dope poly Si (poly2), some goes directly onto mmpoly1 being permanently bonded (~ 2.5 µm thick); pattern/etch with mmpoly2.

22. SUMMiT V Process Sequence, continued… So far, all depositions have been conformal, taking the shape of the underlying topography. To proceed further, planarization (CMP) of the subsequent layers will be used to flatten the sacrificial oxide layers. • Deposit ~ 6 µm of oxide (TEOS process) (sacox3) followed by CMP to planarize. Pattern/etch with dimple3_cut for dimples (etch through sacox3) and sacox3_cut for anchors. • Deposit 0.4 µm poly Si to backfill dimple holes. • Deposit ~ 2 µm of doped poly (poly3) on sacox3 layer; pattern/etch with mmpoly3. • Deposit oxide layer (sacox4) & pattern/etch with sacox4_cut and dimple4_cut. • Deposit ~ 2 µm doped poly Si layer (poly4), pattern/etch with mmpoly4. • Release etch to remove all sacrificial oxides using 100:1 HF:HCl. • Drying process to remove wet etch using either air evaporation (for very stiff structures), supercritical CO2 drying (especially for large area devices), or CO2 freeze sublimation.

23. SUMMiT V Material Layers SUMMiT V process uses 5 levels of poly Si and 4 levels of sacrificial oxides. The physical layout looks like this. sacrificial oxide layer thicknesses structural poly Si layer thicknesses sacox4 sacox3 sacox1

24. microchain gears MEMS clock face torsion micromirror array MEMS AFM scanning mechanism probe tip Texas Tech 2005 Sandia MEMS Design Competition winner Includes a micromechanical clock, microchain, torsion micromirror, & micron-sized AFM