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Power Reduction Technique

Power Reduction Technique. Parallelism in circuits using duplication of logic ELEC 6270 By Sreekumar Menon. OUTLINE. Problem Definition Steps for Implementation Background Information Experimental Results Theoretical Results Conclusion Lessons. Problem Definition.

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Power Reduction Technique

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  1. Power Reduction Technique Parallelism in circuitsusing duplication of logic ELEC 6270 By Sreekumar Menon

  2. OUTLINE • Problem Definition • Steps for Implementation • Background Information • Experimental Results • Theoretical Results • Conclusion • Lessons

  3. Problem Definition • Design a 32 bit adder with parallelism • Operational speed must be the same (throughput constant) • Show it to be an effective Power reduction scheme

  4. Block diagram Representation

  5. Implementation Technique • MODELSim, Leonardo, Design Architect, Eldo • Technology used ami 0.5 • Delay calculation( 50 % of the rise time) • VHDL/Verilog • http://www.amis.com/pdf/process_specifications/c5_ss.pdf

  6. Power versus voltage (N=1)

  7. Dynamic Power v/s Voltage (N=1)

  8. Power versus voltage (N=2)

  9. Dynamic Power v/s Voltage (N=2)

  10. Delay versus Voltage (N=1)

  11. Delay versus Voltage (N=1)

  12. Experimental Results

  13. Power Reductions

  14. Theoretical Calculations • Power = CVDD2 • The Delay versus Voltage graph can be used for interpolating the voltage levels for various degrees of parallelism

  15. Theoretical v/s Experimental

  16. Conclusions • Parallelism is an effective power reduction technique • However, it causes extra designing effort • The theoretical calculations do not exactly match because the overhead hasn’t been taken into account in it

  17. Lessons • Patience!!!!!!!!!!!!!!!!!!!!!!!!!

  18. References • Dr Agrawal’s website • Mentor manuals

  19. Thank You!!!!!

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