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CMSC 411-101 Computer Architecture Lecture 14 Single-cycle Control Unit March 14, 2001 www.csee.umbc.edu/~younis/CMSC411/ CMSC411.htm. Lecture’s Overview. Previous Lecture: Processor design steps (ISA analysis, component selection, datapath assembly, control unit) Basic building blocks

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Lecture s overview

CMSC 411-101Computer ArchitectureLecture 14Single-cycle Control Unit March 14, 2001www.csee.umbc.edu/~younis/CMSC411/ CMSC411.htm

CMCS 411, Computer Architecture1


Lecture s overview

Lecture’s Overview

  • Previous Lecture:

    • Processor design steps

      (ISA analysis, component selection, datapath assembly, control unit)

    • Basic building blocks

    • (Register files, adders, multiplexers)

    • Building a datapath

      (Instruction fetch, register transfer requirements)

  • This Lecture:

    • Control unit design

    • Single cycle processor

    • Circuit implementation of control unit

CMCS 411, Computer Architecture2


Lecture s overview

Summary of Previous Lecture

Computer

Processor

Memory

Devices

Control

Input

Datapath

Output

Design Steps:

1. Analyze instruction set => datapath requirements

2. Select set of datapath components and establish

clocking methodology

3.Assemble datapath meeting the requirements

4. Analyze implementation of each instruction to determine

setting of control points that effects the register transfer

5. Assemble the control logic

  • Last class

  • This class

Coordination for proper operation

  • This class

Connections for Information flow

  • Last class

CMCS 411, Computer Architecture3


Lecture s overview

Single-cycle Datapath

Instruction<31:0>

nPC_sel

Instruction

Fetch Unit

Rd

Rt

<0:15>

<21:25>

<16:20>

<11:15>

Clk

RegDst

1

0

Mux

Rt

Rs

Rd

Imm16

Rs

Rt

RegWr

ALUctr

5

5

5

MemtoReg

busA

Zero

MemWr

Rw

Ra

Rb

busW

32

32 32-bit

Registers

0

ALU

32

busB

32

0

Clk

Mux

32

Mux

32

1

WrEn

Adr

1

Data In

32

Data

Memory

Extender

imm16

32

16

Clk

ALUSrc

ExtOp

  • Today’s lecture will show you how to generate the control signals (underline)

* Slide is courtesy of Dave Patterson

CMCS 411, Computer Architecture4


Lecture s overview

Instruction Fetch Unit

Instruction<31:0>

Instruction<31:0>

Inst

Memory

Inst

Memory

Adr

Adr

nPC_sel

nPC_sel

4

4

00

Adder

Adder

00

PC

PC Ext

Mux

Mux

PC

Clk

imm16

Adder

Adder

Clk

imm16

PC Ext

Instruction  mem[PC]

same for all instructions

PC  PC + 4

same for all instructions except: Branch & Jump

* Figures are courtesy of Dave Patterson

CMCS 411, Computer Architecture5


Lecture s overview

Single Cycle Datapath during Add

31

26

21

16

11

6

0

op

rs

rt

rd

shamt

funct

R[rd]  R[rs] + R[rt]

Instruction<31:0>

nPC_sel= +4

Instruction

Fetch Unit

Rd

Rt

<0:15>

<21:25>

<16:20>

<11:15>

Clk

RegDst = 1

1

0

Mux

ALUctr = Add

Rt

Rs

Rd

Imm16

Rs

Rt

RegWr = 1

5

5

5

MemtoReg = 0

busA

Zero

MemWr = 0

Rw

Ra

Rb

busW

32

32 32-bit

Registers

0

ALU

32

busB

32

0

Clk

Mux

32

Mux

32

1

WrEn

Adr

1

Data In

32

Data

Memory

Extender

imm16

32

16

Clk

ALUSrc = 0

ExtOp = x

* Slide is courtesy of Dave Patterson

CMCS 411, Computer Architecture6


Lecture s overview

Datapath during Or Immediate

31

26

21

16

0

op

rs

rt

immediate

Instruction<31:0>

nPC_sel =

Instruction

Fetch Unit

Rd

Rt

<0:15>

<21:25>

<16:20>

<11:15>

Clk

RegDst =

1

0

Mux

Rt

Rs

Rd

Imm16

Rs

Rt

ALUctr =

RegWr =

5

5

5

MemtoReg =

busA

Zero

MemWr =

Rw

Ra

Rb

busW

32

32 32-bit

Registers

0

ALU

32

busB

32

0

Clk

Mux

32

Mux

32

1

WrEn

Adr

1

Data In

32

Data

Memory

Extender

imm16

32

16

Clk

ALUSrc =

ExtOp =

R[rt]  R[rs] or ZeroExt[Imm16]

* Slide is courtesy of Dave Patterson

CMCS 411, Computer Architecture7


Lecture s overview

Datapath during Or Immediate

31

26

21

16

0

op

rs

rt

immediate

R[rt]  R[rs] or ZeroExt[Imm16]

Instruction<31:0>

nPC_sel= +4

Instruction

Fetch Unit

Rd

Rt

<0:15>

<21:25>

<16:20>

<11:15>

Clk

RegDst = 0

1

0

Mux

Rt

Rs

Rd

Imm16

Rs

Rt

ALUctr = Or

RegWr = 1

MemtoReg = 0

5

5

5

busA

Zero

MemWr = 0

Rw

Ra

Rb

busW

32

32 32-bit

Registers

0

ALU

32

busB

32

0

Clk

Mux

32

Mux

32

1

WrEn

Adr

1

Data In

32

Data

Memory

Extender

imm16

32

16

Clk

ALUSrc = 1

ExtOp = 0

* Slide is courtesy of Dave Patterson

CMCS 411, Computer Architecture8


Lecture s overview

Single Cycle Datapath during Load

31

26

21

16

0

op

rs

rt

immediate

R[rt]  Data Memory {R[rs] + SignExt[imm16]}

Instruction<31:0>

nPC_sel= +4

Instruction

Fetch Unit

Rd

Rt

<0:15>

<21:25>

<16:20>

<11:15>

Clk

RegDst = 0

1

0

Mux

Rt

Rs

Rd

Imm16

Rs

Rt

ALUctr = Add

RegWr = 1

MemtoReg = 1

5

5

5

busA

Zero

MemWr = 0

Rw

Ra

Rb

busW

32

32 32-bit

Registers

0

ALU

32

busB

32

0

Clk

Mux

32

Mux

1

WrEn

Adr

1

Data In

32

Data

Memory

Extender

32

imm16

32

16

Clk

ALUSrc = 1

ExtOp = 1

* Slide is courtesy of Dave Patterson

CMCS 411, Computer Architecture9


Single cycle datapath during store

Single Cycle Datapath during Store

31

26

21

16

0

op

rs

rt

immediate

Instruction<31:0>

nPC_sel =

Instruction

Fetch Unit

Rd

Rt

<0:15>

<21:25>

<16:20>

<11:15>

Clk

RegDst =

1

0

Mux

Rt

Rs

Rd

Imm16

Rs

Rt

ALUctr =

RegWr =

5

5

5

MemtoReg =

busA

Zero

MemWr =

Rw

Ra

Rb

busW

32

32 32-bit

Registers

0

ALU

32

busB

32

0

Clk

Mux

32

Mux

32

1

WrEn

Adr

1

Data In

32

Data

Memory

Extender

imm16

32

16

Clk

ALUSrc =

ExtOp =

Data Memory {R[rs] + SignExt[imm16]}  R[rt]

* Slide is courtesy of Dave Patterson

CMCS 411, Computer Architecture10


Single cycle datapath during store1

Single Cycle Datapath during Store

31

26

21

16

0

op

rs

rt

immediate

Data Memory {R[rs] + SignExt[imm16]}  R[rt]

Instruction<31:0>

nPC_sel= +4

Instruction

Fetch Unit

Rd

Rt

<21:25>

<16:20>

<11:15>

<0:15>

Clk

RegDst = x

1

0

Mux

ALUctr = Add

Rt

Rs

Rd

Imm16

Rs

Rt

RegWr = 0

5

5

5

MemtoReg = x

busA

Zero

MemWr = 1

Rw

Ra

Rb

busW

32

32 32-bit

Registers

0

ALU

32

busB

32

0

Clk

Mux

32

Mux

32

1

WrEn

Adr

1

32

Data In

Data

Memory

Extender

imm16

32

16

Clk

ALUSrc = 1

ExtOp = 1

* Slide is courtesy of Dave Patterson

CMCS 411, Computer Architecture11


Single cycle datapath during branch

Single Cycle Datapath during Branch

31

26

21

16

0

op

rs

rt

immediate

if (R[rs] - R[rt] == 0) then Zero  1 ; else Zero  0

Instruction<31:0>

nPC_sel= “Br”

Instruction

Fetch Unit

Rd

Rt

<21:25>

<16:20>

<11:15>

<0:15>

Clk

RegDst = x

1

0

Mux

ALUctr = Subtract

Rt

Rs

Rd

Imm16

Rs

Rt

RegWr = 0

MemtoReg = x

5

5

5

busA

Zero

MemWr = 0

Rw

Ra

Rb

busW

32

32 32-bit

Registers

0

ALU

32

busB

32

0

Clk

Mux

32

Mux

32

1

WrEn

Adr

1

Data In

32

Data

Memory

Extender

imm16

32

16

Clk

ALUSrc = 0

ExtOp = x

* Slide is courtesy of Dave Patterson

CMCS 411, Computer Architecture12


Instruction fetch unit at end of branch

Instruction Fetch Unit at End of Branch

31

26

21

16

0

op

rs

rt

immediate

Inst

Memory

Instruction<31:0>

Adr

nPC_sel

4

00

Adder

PC

Mux

Clk

Adder

imm16

PC Ext

if (Zero == 1) then

PC = PC + 4 + SignExt[imm16]*4 ;

else PC = PC + 4

* Slide is courtesy of Dave Patterson

CMCS 411, Computer Architecture13


Step 4 given datapath rtl control

Step 4: Given Datapath: RTL  Control

Instruction<31:0>

Inst

Memory

<21:25>

<0:15>

<21:25>

<16:20>

<11:15>

Adr

Op

Fun

Rt

Rs

Rd

Imm16

Control

ALUctr

nPC_sel

MemWr

MemtoReg

ALUSrc

RegWr

RegDst

ExtOp

Equal

DATA PATH

* Slide is courtesy of Dave Patterson

CMCS 411, Computer Architecture14


Value of control signals

Value of Control Signals

inst Register Transfer

ADDR[rd]  R[rs] + R[rt];PC  PC + 4

ALUsrc = RegB, ALUctr = “add”, RegDst = rd, RegWr, nPC_sel = “+4”

SUBR[rd]  R[rs] – R[rt];PC  PC + 4

ALUsrc = RegB, ALUctr = “sub”, RegDst = rd, RegWr, nPC_sel = “+4”

ORiR[rt]  R[rs] + zero_ext(Imm16); PC  PC + 4

ALUsrc = Im, Extop = “Z”, ALUctr = “or”, RegDst = rt, RegWr, nPC_sel = “+4”

LOADR[rt]  MEM[ R[rs] + sign_ext(Imm16)];PC  PC + 4

ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemtoReg, RegDst = rt, RegWr, nPC_sel = “+4”

STOREMEM[ R[rs] + sign_ext(Imm16)]  R[rs];PC  PC + 4

ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemWr, nPC_sel = “+4”

BEQif ( R[rs] == R[rt] ) then PC PC + sign_ext(Imm16)] || 00 else PC  PC + 4

nPC_sel = “Br”, ALUctr = “sub”

* Slide is courtesy of Dave Patterson

CMCS 411, Computer Architecture15


A summary of the control signals

A Summary of the Control Signals

See

func

10 0000

10 0010

We Don’t Care :-)

Appendix A

op

00 0000

00 0000

00 1101

10 0011

10 1011

00 0100

00 0010

add

sub

ori

lw

sw

beq

jump

RegDst

1

1

0

0

x

x

x

0

0

1

1

1

0

ALUSrc

x

MemtoReg

0

0

0

1

x

x

x

1

1

1

1

0

0

RegWrite

0

0

0

0

0

1

0

0

MemWrite

nPCsel

0

0

0

0

0

1

0

0

0

0

0

0

0

1

Jump

ExtOp

x

x

0

1

1

x

x

Add

Subtract

Or

Add

Add

ALUctr<2:0>

xxx

Subtract

31

26

21

16

11

6

0

op

rs

rt

rd

shamt

funct

immediate

op

rs

rt

op

target address

R-type

add, sub

I-type

ori, lw, sw, beq

J-type

jump

* Slide is courtesy of Dave Patterson

CMCS 411, Computer Architecture16


The concept of local decoding

The Concept of Local Decoding

op

00 0000

00 1101

10 0011

10 1011

00 0100

00 0010

R-type

ori

lw

sw

beq

jump

RegDst

1

0

0

x

x

x

ALUSrc

0

1

1

1

0

x

MemtoReg

0

0

1

x

x

x

RegWrite

1

1

1

0

0

0

MemWrite

0

0

0

1

0

0

Branch

0

0

0

0

1

0

Jump

0

0

0

0

0

1

ExtOp

x

0

1

1

x

x

ALUop<N:0>

“R-type”

Or

Add

Add

xxx

Subtract

func

ALUctr

ALU

Control

(Local)

op

6

Main

Control

3

ALUop

6

N

ALU

* Slide is courtesy of Dave Patterson

CMCS 411, Computer Architecture17


Encoding of aluop

Encoding of ALUop

func

ALU

Control

(Local)

op

6

ALUctr

Main

Control

ALUop

6

3

N

R-type

ori

lw

sw

beq

jump

ALUop (Symbolic)

“R-type”

Or

Add

Add

xxx

Subtract

ALUop<2:0>

1 00

0 10

0 00

0 00

xxx

0 01

  • In this exercise, ALUop has to be 2 bits wide to represent:

    • (1) “R-type” instructions

    • “I-type” instructions that require the ALU to perform:

      (2) Or, (3) Add, and (4) Subtract

  • To implement the full MIPS ISA, ALUop has to be 3 bits for:

    • (1) “R-type” instructions

    • “I-type” instructions that require the ALU to perform:

      (2) Or, (3) Add, (4) Subtract, and (5) And (Example: andi)

* Slide is courtesy of Dave Patterson

CMCS 411, Computer Architecture18


Decoding of the func field

Decoding of the “func” Field

func

ALU

Control

(Local)

op

6

ALUctr

Main

Control

ALUop

6

3

N

R-type

ori

lw

sw

beq

jump

ALUop (Symbolic)

“R-type”

Or

Add

Add

xxx

Subtract

ALUop<2:0>

1 00

0 10

0 00

0 00

xxx

0 01

31

26

21

16

11

6

0

R-type

op

rs

rt

rd

shamt

funct

funct<5:0>

Instruction Operation

ALUctr

ALUctr<2:0>

ALU Operation

10 0000

add

000

Add

10 0010

subtract

001

Subtract

10 0100

and

010

And

ALU

10 0101

or

110

Or

10 1010

set-on-less-than

111

Set-on-less-than

* Slide is courtesy of Dave Patterson

CMCS 411, Computer Architecture19


The truth table for aluctr

The Truth Table for ALUctr

R-type

ori

lw

sw

beq

ALUop

(Symbolic)

“R-type”

Or

Add

Add

Subtract

ALUop<2:0>

1 00

0 10

0 00

0 00

0 01

ALUop

func

ALU

Operation

ALUctr

bit<2>

bit<1>

bit<0>

bit<3>

bit<2>

bit<1>

bit<0>

bit<2>

bit<1>

bit<0>

0

0

0

x

x

x

x

Add

0

1

0

0

x

1

x

x

x

x

Subtract

1

1

0

0

1

x

x

x

x

x

Or

0

0

1

1

x

x

0

0

0

0

Add

0

1

0

1

x

x

0

0

1

0

Subtract

1

1

0

1

x

x

0

1

0

0

And

0

0

0

1

x

x

0

1

0

1

Or

0

0

1

1

x

x

1

0

1

0

Set on <

1

1

1

funct<3:0>

Instruction Op.

0000

add

0010

subtract

0100

and

0101

or

1010

set-on-less-than

* Slide is courtesy of Dave Patterson

CMCS 411, Computer Architecture20


The logic equation for aluctr

The Logic Equation for ALUctr

ALUop

func

bit<2>

bit<1>

bit<0>

bit<3>

bit<2>

ALU

Control

(Local)

bit<1>

bit<0>

ALUctr<2>

0

x

1

x

x

x

x

1

1

x

x

0

0

1

0

1

1

x

x

1

0

1

0

1

This makes func<3> a don’t care

ALUctr<2> = !ALUop<2> & ALUop<0> +

ALUop<2> & !func<2> & func<1> & !func<0>

Similarly:

ALUctr<1> = !ALUop<2> & !ALUop<1> +

ALUop<2> & !func<2> & !func<0>

ALUctr<0> = !ALUop<2> & ALUop<0>

+ ALUop<2> & !func<3> & func<2> & !func<1> & func<0>

+ ALUop<2> & func<3> & !func<2> & func<1> & !func<0>

func

6

ALUctr

ALUop

3

3

* Slide is courtesy of Dave Patterson

CMCS 411, Computer Architecture21


Step 5 logic for each control signal

Step 5: Logic for each control signal

  • nPC_sel  if (OP == BEQ) then EQUAL else 0

  • ALUsrc  if (OP == “Rtype”) then “regB” else “immed”

  • ALUctr  if (OP == “Rtype”) then funct elseif (OP == ORi) then “OR” elseif (OP == BEQ) then “sub” else “add”

  • ExtOp 

  • MemWr 

  • MemtoReg 

  • RegWr: 

  • RegDst: 

if (OP == ORi) then “zero” else “sign”

(OP == Store)

(OP == Load)

if ((OP == Store) || (OP == BEQ)) then 0 else 1

if ((OP == Load) || (OP == ORi)) then 0 else 1

* Slide is courtesy of Dave Patterson

CMCS 411, Computer Architecture22


Truth table for the main control

“Truth Table” for the Main Control

RegDst

func

ALUSrc

ALUctr

ALU

Control

(Local)

op

6

Main

Control

:

3

6

ALUop

3

op

00 0000

00 1101

10 0011

10 1011

00 0100

00 0010

R-type

ori

lw

sw

beq

jump

RegDst

1

0

0

x

x

x

ALUSrc

0

1

1

1

0

x

MemtoReg

0

0

1

x

x

x

RegWrite

1

1

1

0

0

0

MemWrite

0

0

0

1

0

0

Branch

0

0

0

0

1

0

Jump

0

0

0

0

0

1

ExtOp

x

0

1

1

x

x

ALUop (Symbolic)

“R-type”

Or

Add

Add

xxx

Subtract

ALUop <2>

1

0

0

0

x

0

ALUop <1>

0

1

0

0

x

0

ALUop <0>

0

0

0

0

x

1

* Slide is courtesy of Dave Patterson

CMCS 411, Computer Architecture23


The truth table for regwrite

The “Truth Table” for RegWrite

op

00 0000

00 1101

10 0011

10 1011

00 0100

00 0010

R-type

ori

lw

sw

beq

jump

RegWrite

1

1

1

0

0

0

.

.

.

.

.

.

op<5>

op<5>

op<5>

op<5>

op<5>

op<5>

.

.

.

.

.

.

<0>

<0>

<0>

<0>

<0>

op<0>

R-type

ori

lw

sw

beq

jump

RegWrite

RegWrite = R-type + ori + lw

= !op<5> & !op<4> & !op<3> & !op<2> & !op<1> & !op<0>(R-type)

+ !op<5> & !op<4> & op<3> & op<2> & !op<1> & op<0>(ori)

+ op<5> & !op<4> & !op<3> & !op<2> & op<1> & op<0>(lw)

* Slide is courtesy of Dave Patterson

CMCS 411, Computer Architecture24


Implementation of the main control

Implementation of the Main Control

.

.

.

.

.

.

op<5>

op<5>

op<5>

op<5>

op<5>

op<5>

.

.

.

.

.

.

<0>

<0>

<0>

<0>

<0>

op<0>

R-type

ori

lw

sw

beq

jump

RegWrite

ALUSrc

RegDst

MemtoReg

MemWrite

Branch

Jump

ExtOp

ALUop<2>

ALUop<1>

ALUop<0>

* Slide is courtesy of Dave Patterson

CMCS 411, Computer Architecture25


A single cycle processor

A Single Cycle Processor

ALUop

ALU

Control

ALUctr

3

RegDst

func

op

3

Main

Control

Instr<5:0>

6

ALUSrc

6

:

Instr<31:26>

Instruction<31:0>

nPC_sel

Instruction

Fetch Unit

Rd

Rt

<0:15>

<21:25>

<16:20>

<11:15>

Clk

RegDst

1

0

Mux

Rt

Rs

Rd

Imm16

Rs

Rt

RegWr

ALUctr

5

5

5

MemtoReg

busA

Zero

MemWr

Rw

Ra

Rb

busW

32

32 32-bit

Registers

0

ALU

32

busB

32

0

Clk

Mux

32

Mux

32

1

WrEn

Adr

1

Data In

32

Data

Memory

Extender

imm16

32

16

Instr<15:0>

Clk

ALUSrc

ExtOp

CMCS 411, Computer Architecture26


Worst case timing load

Worst Case Timing (Load)

Clk

Clk-to-Q

Old Value

New Value

PC

Instruction Memoey Access Time

Rs, Rt, Rd,

Op, Func

Old Value

New Value

Delay through Control Logic

ALUctr

Old Value

New Value

ExtOp

Old Value

New Value

ALUSrc

Old Value

New Value

MemtoReg

Old Value

New Value

Register

Write Occurs

RegWr

Old Value

New Value

Register File Access Time

busA

Old Value

New Value

Delay through Extender & Mux

busB

Old Value

New Value

ALU Delay

Address

Old Value

New Value

Data Memory Access Time

busW

Old Value

New

CMCS 411, Computer Architecture27


Conclusion

Conclusion

  • Summary

    • Control unit design

      (Steps of control design, register transfer logic)

    • Single cycle processor

      (Advantage and disadvantage, integration of datapath and control)

    • Circuit implementation of control unit

      (Logic equations, truth tables, combinational circuit)

  • Next Lecture

    • Multi-cycle datapath

    • Sequencer design

    • Multi-cycle control

Reading assignment includes sections 5.3 in the text book

CMCS 411, Computer Architecture28


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