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Developments of HV-CMOS pixel sensors

Developments of HV-CMOS pixel sensors. Ivan Peri ć for HVCMOS collaboration. Overview. High-voltage CMOS pixel sensors - introduction Summary of the old results HV-CMOS for LHC and CLIC. High-voltage CMOS pixel detectors or “smart diode arrays” or “HV-MAPS”. HV CMOS detectors.

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Developments of HV-CMOS pixel sensors

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  1. Developments of HV-CMOS pixel sensors Ivan Perić for HVCMOS collaboration

  2. Overview • High-voltage CMOS pixel sensors -introduction • Summary of the old results • HV-CMOS for LHC and CLIC

  3. High-voltage CMOS pixel detectorsor “smart diode arrays” or “HV-MAPS”

  4. HV CMOS detectors • We start with a low voltage process: • PMOS and NMOS transistors are placed inside the shallow n- and p-wells. Pixel 2 Pixel 1 Pixel 3 PMOS NMOS Shallow n-well Shallow p-well

  5. HV CMOS detectors • A deep n-well surrounds the electronics of every pixel. Pixel 2 Pixel 1 Pixel 3 PMOS NMOS deep n-well

  6. HV CMOS detectors • The deep n-wells isolate the pixel electronics from the p-type substrate. Pixel 2 Pixel 1 Pixel 3 PMOS NMOS deep n-well p-substrate

  7. HV CMOS detectors • The substrate can be biased low without damaging the transistors. • In this way the depletion zones in the volume around the n-wells are formed. • => Potential minima for electrons PMOS NMOS deep n-well Potential energy (e-) Depletionzone p-substrate

  8. HV CMOS detectors • Charge collection occurs by drift. (main part of the signal) PMOS NMOS deep n-well Drift Potential energy (e-) Depletionzone p-substrate

  9. HV CMOS detectors • Charge collection occurs by drift. (main part of the signal) • Additional charge collection by diffusion PMOS NMOS deep n-well Drift Potential energy (e-) Depletionzone p-substrate Diffusion

  10. HV CMOS detectors • HVCMOS sensors can be implemented in any CMOS technology that has a deep-n-well surrounding low voltage p-wells. (e.g. LV UMC 180nm.) • Maximizing of the depleted regions improves performances (less capacitance and noise, more signal) – the best results can be achieved in high-voltage technologies: • These technologies (usually) use deeper n-wells and the substrates of higher resistances than the LV CMOS. Smart diode PMOS NMOS deep n-well Potential energy (e-) Depletionzone p-substrate

  11. HV CMOS detectors • Example AMS 350nm HVCMOS: Typical reverse bias voltage is 60-100 V and the depleted region depth ~15 m. • 20 cm substrate resistance -> acceptor density ~ 1015 cm-3. PMOS NMOS deep n-well 100V ~15µm Depletionzone

  12. Capacitively Coupled Pixel DetectorsCCPDs

  13. Standard hybrid detector Pixel Readout chip Min. pitch ~50 μm Bumps Charge signal is transmitted Fully-depleted sensor Signal charge

  14. CCPD with a “passive” sensor Pixel Readout chip Min. pitch < 50 μm Voltage signal is transmitted Requires bias resistors on the sensor Can be implemented as punch-through structure Signal ~30mV for 250µm thick sensor (Cdet = 100fF) Operation with thin sensors is problematic. Fully-depleted sensor Signal charge

  15. Active CCPD Pixel Readout chip Sensor implemented as HVCMOS sensor Advantage: Charge to voltage amplification on the sensor chip Typical voltage signal ~100mV Easier capacitive transmission Can be thinned without signal loss Smart diode- or fully-depleted sensor Signal charge Signal >30mV for very thin sensors

  16. Project results

  17. Project history 2006 „Proof of principle“ phase 350nm AMS HV technology Simple signal integrating pixels with pulsed reset and rolling shutter RO. (Possible applications: ILC, transmission electron microscopy, etc.) 2) Pixels with complex CMOS-based pixel electronics that detect particle signals. (Possible applications: CLIC, LHC, CBM, etc.) 3) Capacitively coupled pixel detectors (CCPDs) based on a pixel sensor implemented as a smart diode array.

  18. Test-beam results Efficiency at TB: ~98% (probably due to rolling shutter effects Seed pixel SNR 27, seed signal 1200e, cluster 2000e Rolling shutter readout detector: HVPixelM: 21x21 µm pixel size Spatial resolution 3-3.8µm

  19. CCPD – signal and noise Pixel matrix efficiency: Detection of signals > 350e possible MIP signal ~ 1800 e CAPPIX/CAPSENSE edgeless CCPD 50x50 µm pixel size Noise 30-40e Time resolution 300ns MIP SNR 45-60

  20. CCPD - irradiations Readout chip Digital part A A Sensor CAPPIX/CAPSENSE edgeless CCPD 50x50 µm pixel size

  21. Irradiation with protons at KIT (1015neq/cm2, 300 MRad) 55Fe spectrum and RMS noise Not irradiated Room temperature RMS Noise 12 e 55Fe spectrum and RMS noise Irradiated 20C RMS Noise 270 e 55Fe 55Fe peak Noise peak Base line noise (RMS) Base line noise (RMS) 55Fe spectrum, RMS noise Irradiated 10C RMS Noise 77 e 55Fe spectrum, RMS noise Irradiated -10C RMS Noise 40 e

  22. Irradiation with protons at KIT (1015neq/cm2, 300 MRad) 55Fe 55Fe and 22Na spectrum, RMS noise Irradiated Temperature 10C RMS Noise 77 e SNR = 64 22Na 55Fe and 22Na spectrum, RMS noise Irradiated Temperature 20C RMS Noise 270 e SNR = 15 55Fe and 22Na spectrum, RMS noise Irradiated Temperature -10C RMS Noise 40 e SNR = 93

  23. Irradiation with protons at KIT (1015neq/cm2, 300 MRad) -60V 0V -30V 22Na 55Fe

  24. New projects 65nm UMCLV technology 2006 „Proof of principle“ phase 180nm AMS HV technology 350nm AMS HV technology Applications: 1) ATLAS and CLIC Smart sensors readout by pixel- and strip –readout chips. 2) Mu3e experiment at PSI Monolithic pixel detector 3) Transmission electron microscopy integrating pixels with pulsed reset and rolling shutter RO – in-pixel CDS

  25. Sensor concepts • Pixel electronics is based on a charge-sensitive amplifier and optionally a comparator. • The pixel signal/address is sent as an analog information. • The pixel-signal is processed by the digital circuits are on the chip periphery or on a separate chip. • 1) Mu3e: The pixel signal is processed on the sensor chip itself -> monolithic pixel detector. • 2) ATLAS: intelligent sensor concept. The pixel address is transmitted to an existing readout chip, like FEI4 or an strip-readout chip. ATLAS: Readout Electronics Mu3e: Readout Electronics Pixels

  26. High-Voltage CMOS Detectors for ATLAS

  27. Strip-like Concept

  28. Comparator or ADC Pixel detector compatible to strip-readout electronics • The present LHC strip detectors consist of large-area strip sensors that are connected by wire bonds to multi-channel ASICs • We use the strip readout ASIC for the readout of the HV sensor Wire-bonds ReadoutASIC Strip sensor Strip CSA

  29. Comparator or ADC Pixel detector compatible to strip-readout electronics • We replace a strip with an array of pixels Wire-bonds ReadoutASIC Pixels CMOS sensor CSA

  30. Comparator or ADC Pixel detector compatible to strip-readout electronics • Pixel electronics is based on a charge-sensitive amplifier and a comparator. • Pixel electronics generate a digital current pulse with an unique amplitude. • The pixel outputs (currents) are summed, converted to voltage signal and transmitted to readout ASIC by means of AC coupling. Summing line Wire-bonds ReadoutASIC Pixels CMOS sensor CSA A

  31. Pixel detector compatible to strip-readout electronics • A large area CMOS sensor can be produced by stitching several 2cm x 2cm wafer reticles. • Any arbitrary pixel group pattern is possible. • Advantages: • Commercial sensor technology – lower price per unit area. • Intrinsic 2D spatial resolution • No need for bias voltages higher than 60V. • Operation at temperatures above 0C is according to tests possible (irradiations to 1015neq/cm2). • Thinning possible.

  32. Disadvantages: Pileup • Two hits close in time within one strip can lead to corrupted address information. • The effect can be reduced by filtering. • Pileup if hit-coincidence ~100ns. Summingline 1 µs Pixel1 Pixel2 A 100ns

  33. Can we apply the Strip-like Concept in the case of high particle flux?Hit-Occupancy and Efficiency

  34. Improved RO-scheme for better efficiency • Improved (bus still simple) readout schemes are possible to improve efficiency. • The modified scheme works for 2 hits per array. 8 x I0 8 x I0 2 x I0 5 x I0 2 x I0 3 x I0

  35. Improved scheme for better efficiency • Efficiency for 100 x 100 micrometer pixels and 128 pixels in one array. • Example: for particle flux 8 particles / cm2 / 25ns efficiency is 99.2%. • Inefficiency ~ probability to have > 2 coincident hits (~100ns) in an array. Hit probability per 128 pixel array and 100ns Sum Zero hit probability Single-hit probability Double-hit probability

  36. Pixel Trigger

  37. Simultaneous readout from two 2D sensitive layers • Simultaneous readout from two 2D sensitive layers. Signals from two sensor layers can be easily combined in a single readout ASIC. Sensor layer2 Sensor layer1 Readoutchip Comparator + ADC

  38. Simultaneous readout from two 2D sensitive layers • Detector mechanics: thin sensors can be bent around a carrier structure. • Spacers (~1mm) between sensor layers. • Pixel arrays in φ-direction.

  39. CCPD Concept

  40. CCPD for ATLAS pixel detector • We use FEI4 chip for the readout of an intelligent HVCMOS sensor. • The HV CMOS sensor pixels are smaller than the standard ATLAS pixels, in our case 33μm x 125μm - so that three such pixels cover the area of the original pixel. • The HV pixels contain low-power (~ 7μW) CMOS electronics based on a charge sensitive amplifier and a comparator. …the capacitive coupled HV CMOS sensor Pixel readout chip (FE-chip) Pixel electronicsbased on CSA Coupling capacitance Bump-bond pad Glue Summing line Transmitting plate 33x 125 μm Pixel CMOS sensor

  41. CCPD for ATLAS pixel detector • The electronics responds to a particle hit by generating a pulse. • The signals of a few pixels are summed, converted to voltage and transmitted to the charge sensitive amplifier in the corresponding channel of the FE chip using AC coupling. • Each of the pixels that couple to one FE receiver has its unique signal amplitude, so that the pixel can be identified by examining the amplitude information generated in FE chip. • In this way, spatial resolution in - and z-direction can be improved. Pixel readout chip (FE-chip) Pixel electronicsbased on CSA Coupling capacitance Bump-bond pad Glue Summing line Transmitting plate 33x 125 μm Pixel CMOS sensor

  42. Advantages compared to existing detectors • No need for bump-bond connection between the sensor and readout chip – lower price, better mechanical stability, less material • Commercial sensor technology – lower price • No need for bias voltages higher than 60V • Operation at temperatures above 0C is according to tests possible (irradiations to 1015neq/cm2) • Increased spatial resolution (e.g. 25m x 125m binary resolution)with the existing FE chip • Smaller clusters at high incidence angles • Possibility of sensor-thinning without signal loss. Since we do not use bumps and FE chips can be thinned as well, the amount of material would be very low. • Interesting choice for other experiments where low-mass detectors are needed such as CLIC, ILC, CBM, etc...

  43. Test Chip HV2FEI4

  44. HV2FEI4 • Pixel matrix: 60x24 pixels • Pixel size 33 m x 125 m • 21 IO pads at the lower side for CCPD operation • 40 strip-readout pads (100 m pitch) at the lower side and 22 IO pads at the upper side for strip-operation • Pixel contains charge sensitive amplifier, comparator and tune DAC. IO pads for strip operation Pixel matrix 4.4mm Strip pads IO padsfor CCPD operation

  45. Strip-like Readout Amplitude 3 Amplitude 2 Amplitude 1 Pad Pad

  46. CCPD Readout FEI4 Pixels Signal transmitted capacitively CCPD Pixels 2 2 Bias A 3 3 Bias B 1 1 Bias C

  47. 6 Pixels – Layout Tune DAC Comparator Amplifier 33 µm

  48. Experimental results(strip readout)

  49. Strip-like readout “Hit-bus” operation – 55Fe signals – three pixel columns (each 24 pixels) readout in parallel The amplitude is set to be equal for every pixel Strip like operation – 55Fe signals – three pixel columns (each 24 pixels) readout in parallel The amplitude depends on pixel position

  50. Strip-like readout “Hit-bus” operation – 22Na signals – one pixel columns (24 pixels) readout in parallel The amplitude is set to be equal for every pixel - values around 50mV . “Hit-bus” operation – 22Na signals – one pixel columns (24 pixels) readout in parallel The amplitude depends on pixel position .

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