chapter 4
Download
Skip this Video
Download Presentation
Chapter 4

Loading in 2 Seconds...

play fullscreen
1 / 31

Chapter 4 - PowerPoint PPT Presentation


  • 108 Views
  • Uploaded on

Chapter 4. Instruction Set. Instruction Set Overview. PIC18F4520 devices incorporate the standard set of: 75 PIC18 core instructions, 8 extended set of instructions, f or the optimization of code. Standard Instruction Set. The standard PIC18 instruction set are :

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about ' Chapter 4' - abba


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
chapter 4
Chapter 4

Instruction Set

instruction set overview
Instruction Set Overview
  • PIC18F4520 devices incorporate the standard set of:
    • 75 PIC18 core instructions,
    • 8 extended set of instructions, for the optimization of code
standard instruction set
Standard Instruction Set
  • The standard PIC18 instruction set are :
    • a single program memory word (16 bits), and
    • four instructions that require two program memory locations.
  • Each single-word instruction is a 16-bit word divided into:
    • an opcode, which specifies the instruction type and
    • one or more operands, which further specify the operation of the instruction.
standard instruction set1
Standard Instruction Set
  • The instruction set is grouped into four basic categories:
    • Byte-oriented operations
    • Bit-oriented operations
    • Literal operations
    • Control operations
byte oriented operations
Byte-oriented operations
  • Most Byte-oriented instructions havethree operands:
    • The file register (specified by ‘f’)
    • The destination of the result (specified by ‘d’)
    • The accessed memory (specified by ‘a’)
  • ‘f’ specifies which file register is to be used by the instruction.
  • ‘d’specifies where the result of the operation is to be placed.
    • If ‘d’ is zero, the result is placed in the WREG register.
    • If ‘d’ is one, the result is placed in the file register specified in the instruction.
bit oriented operations
Bit-oriented operations
  • All Bit-oriented instructions have three operands:
    • The file register (specified by ‘f’)
    • The bitin the file register (specified by ‘b’)
    • The accessed memory (specified by ‘a’)
  • ‘b’ selects the number of the bit affected by the operation
  • ‘f’ represents the number of the file in which bit is located.
literal operations
Literal operations
  • The Literal instructions may use some of the following operands:
    • A literal value to be loaded into a file register (specified by ‘k’).
    • The desired FSR register to load the literal value into (specified by ‘f’).
    • No operand required (specified by ‘—’)
control operations
Control operations
  • The Control instructions may use some of the following operands:
    • A program memory address (specified by ‘n’)
    • The mode of the CALL or RETURN instructions (specified by ‘s’)
    • The mode of the table read and table write instructions (specified by ‘m’)
    • No operand required (specified by ‘—’) 
standard instruction set2
Standard Instruction Set
  • All instructions are a single word(16bits), except for four double-word instructions.
    • These double-word instructions were made to contain the required information in 32 bits.
    • In the second word, the 4 MSBs are ‘1’s, if this second word is executed as an instruction (by itself), it will be execute as a NOP.
standard instruction set3
Standard Instruction Set
  • All single-word instructions are executed in a single instruction cycle, unless
    • a conditional test is true or the program counter is changed as a result of the instruction.
    • In these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a NOP.
  • The double-word instructions execute in two instruction cycles.
  • One instruction cycle consists of four oscillator periods.
oscillator frequency
Oscillator Frequency
  • For an oscillator frequency of 4 MHz, the normal instruction execution time is 1 μs.
  • If a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 μs.
  • Two-wordbranch instructions (if true) would take 3 μs.
instruction flow pipelining
Instruction Flow / Pipelining
  • An “Instruction Cycle” consists of four Q cycles: Q1 through Q4.
  • The instruction fetch and execute are pipelined in such a manner that:
    • a fetch takes one instruction cycle,
    • while decode and execute take another instruction cycle.
  • due to pipelining, each instruction effectively executes in one cycle.
  • If an instruction causes the program counter to change (e.g., GOTO), then two cycles are requiredto complete the instruction.
instruction flow pipelining2
Instruction Flow / Pipelining
  • A fetch cycle begins with the Program Counter incrementing in Q1.
  • In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in Q1 cycle.
  • This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles.
  • Data memory is read during Q2 (operand read) and written during Q4 (destination write)
instructions in program memory
Instructions in Program Memory
  • The program memory is addressed in bytes.
  • Instructions are stored as two bytes or four bytes in program memory.
  • The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSB = 0).
  • To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSB will always read ‘0’.
two word four bytes instruction
Two-Word (four bytes) Instruction
  • The standard PIC18 instruction set has 4 two-word instructions:
    • CALL
    • MOVFF
    • GOTO
    • LSFR.
  • The entire data memory may be accessed by :
    • Direct,
    • Indirect or
    • Indexed Addressing modes.
data addressing modes
Data Addressing Modes
  • The addressing modes are:
    • Inherent
    • Literal
    • Direct
    • Indirect
  • An additional addressing mode, Indexed Literal Offset, is available when the extended instruction set is enabled (XINST Configuration bit = 1).
inherent addressing
Inherent Addressing
  • Do not need any argument at all
  • They either perform an operation that globally affects the device or they operate implicitly on one register.
  • Examples include SLEEP, RESET and DAW.
literal addressing
Literal Addressing
  • Require an additional explicit argument in the opcode.
  • They require some literal value as an argument.
  • Examples are ADDLW and MOVLW, which, add or move a literal value to the W register.
  • CALL and GOTO, which include a 20-bit program memory address.
direct addressing
Direct Addressing
  • Specifies all or part of the source and/or destination address of the operation within the opcode itself.
  • Bit-oriented and Byte oriented instructions use some version of Direct Addressing by default.
  • The address specifies a register address in one of the banks of data RAM or a location in the Access Bank as the data source for the instruction.
  • The Access RAM bit ‘a’ determines how the address is interpreted.
indirect addressing
Indirect Addressing
  • Allows the user to access a location in data memory without giving a fixed address in the instruction.
  • This is done by using File Select Registers (FSRs) as pointers to the locations to be read or written to.
  • Since the FSRs are themselves located in RAM as Special Function Registers, they can also be directly manipulated under program control.
  • This makes FSRs very useful in implementing data structures, such as tables and arrays in data memory.
indirect addressing1
Indirect Addressing

Example 5-5: How to clear RAM (BANK 1) using Indirect Addressing

LFSR FSR0, 100h ;

NEXT CLRF POSTINC0 ; Clear IND register then inc ptr

BTFSS FSR0H, 1 ; All done with ; Bank1?

BRA NEXT ; NO, clear next

CONTINUE ; YES, continue

ad