Time-Domain Segmentation based Massively Parallel Simulation

1. Time-Domain Segmentation based Massively Parallel Simulation Bichen Wu Dept. Micro/nano electronics Tsinghua Univ., Beijing, China Email:cunfuwbc@gmail.com Mobile: +86 152 1056 0855

2. Background • On the one hand, transient circuit simulation is time consuming • Sigma-Delta ADC: 71h • SAR ADC: 41h • FLASH ADC: 38h • PLL: 148h • On the other hand, we got strong parallel computing resource • Many core, distributed computing • How can we increase the circuit simulation efficiency with parallel computing?

3. Circuit simulation • Transient circuit simulation is to solve the initial condition problem of the following differential equation • Backward Euler was used to convert the above to sequence of discrete equations

4. Previous parallel circuit simulation • Domain decomposition A New Partitioning Method for Parallel Simulation of VLSI Circuits on Transistor Level（1996） • Parallel numerical integral method WavePipe: Parallel Transient Simulation of Analog and Digital Circuits on Multi-Core Shared-Memory Machines(DAC 2008) • Multi-algorithm parallel Hierarchical Multi-algorithm Parallel Circuit Simulation (TCAD 2011)

5. Time domain segmentation based parallel simulation t0 tend • Method description t0 t1 t2

6. Time domain segmentation based parallel simulation • In general, solution of equation is dependent on initial condition • Uncertainty brought by time domain segmentation may leads to erroneous result

7. Short memory assumption • Short memory：the state of the circuit at a certain time point is correlated only to the a limited history of the the input as well as the internal state of the circuit. • Circuits such asADC，possess short memory property A Analog input Digital output D

8. Calculating SNDR through transient simulation for ADC Fourier Transform Power spectrum density A Analog input Digital output D

9. Two examples 5bits FLASH ADC Fsam=3.75GHz, Ttotal=2us, Tov=6ns Time for serial simulation：38h Number of segmentation：1，2，4，8，100 6bits SAR ADC Fsam=2GHz, Ttotal=8us, Tov=13.3ns Time for serial simulation：41h Number of segmentation：1，2，4，8，100

10. Transient simulation for ADC Power spectrum density of FLASH ADC(left) and SAR ADC（right）output, with serial and parallel simulation FLASH SAR

11. Transient simulation for ADC • Result

12. Transient simulation for Sigma-Delta ADC • Sigma-Delta modulator Because of integrator, it’s not short memory

13. Transient simulation for Sigma-Delta ADC • Direct segmentation with the modulator output of modulator brings erroneous result Time domain deviation between serial and parallel result Frequency domain deviation between serial and parallel result

14. Transient simulation for Sigma-Delta ADC • Uncertainty brought by time domain segmentation

15. Transient simulation for Sigma-Delta ADC • Solution: Digital filter realized in matlab

16. Transient simulation for Sigma-Delta ADC • Result showed efficiency enhancement with high accuracy

17. Transient simulation for PLL • Phase lock loop(PLL) is not short memory circuit • Self-driven system • Integral property f[ ] h(t) + -

18. Transient simulation for PLL • Phase lock loop(PLL) The expression of the phase growth in the equation above is as follow. Let So we get:

19. Transient simulation for PLL • Phase lock loop(PLL)

20. Transient noise analysis • PSD of 1/f noise generated in serial and parallel The bandwidth gets wider Parallel: Serial

21. Transient noise analysis • 1/f noise in TDSM serial parallel

22. Summary • We proposed TDSM for transient circuit simulation • Testified on FLASH，SAR，Sigma-Delta ADC • Maximum 78X acceleration with 100 cores parallelization • Efficient for phase noise simulation for PLL, testified by behavior model. • Proposed 1/f noise generator that support TDSM, testified on a single transistor • Now submitted to DAC 2013