Coe ee 00142 computer organization set 4 registers datapaths and operations
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CoE - EE 00142 Computer Organization Set 4 Registers, Datapaths and Operations. Ron Hoelzeman. Datapaths & Control Units. Datapath Performs data-processing operations Control unit Determines the sequence of those operations. Control signals. ControlUnit. Status signals. Datapath.

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CoE - EE 00142 Computer Organization Set 4 Registers, Datapaths and Operations

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Coe ee 00142 computer organization set 4 registers datapaths and operations l.jpg

CoE - EE 00142Computer OrganizationSet 4Registers, Datapaths and Operations

Ron Hoelzeman


Datapaths control units l.jpg

Datapaths & Control Units

  • Datapath

    Performs data-processing operations

  • Control unit

    Determines the sequence of those operations


Datapath control unit interaction l.jpg

Control signals

ControlUnit

Status signals

Datapath

Control inputs

Control outputs

Data inputs

Datapath - Control Unit Interaction

Data outputs


Signals l.jpg

Signals

  • Binary signals – one or zero

  • Control signals

    Activate data processing operations in proper sequence

  • Status signals

    Datapath feedback to control unit


Datapaths l.jpg

Datapaths

  • Best defined by registers and operations

  • Examples:

    Shift

    Count

    Load

    clear


Register transfer operations l.jpg

Register Transfer Operations

  • Defined by:

    The set of registers in the system

    The operations performed on the data stored in the registers

    The control that supervises the sequence of operations


Registers l.jpg

Registers

  • Flip Flops

    Review of basics

  • Registers

    Loading

    Shifting


Registers8 l.jpg

Registers

  • Used to store data or instructions

  • Simply adjacent FF’s with loading and other control logic - gates

  • Counters are a special case

  • Sometimes use special names

    accumulators, program counters, index registers, stack pointer, status register, etc.


Register l.jpg

R3

R2

R1

R0

R3

R2

R1

R0

Register

Remember - just a bundle of Flip-Flops


D latch or flip flop l.jpg

Input

Output

Clock

D Latch or Flip Flop

Triggers on positive edge of clock pulse


Concept of synchronization l.jpg

Concept of Synchronization

Triggers on positive edge of clock pulse

Figure 5.2


Concept of synchronization12 l.jpg

Concept of Synchronization

Because of edge trigger, we can feed the output back around to the input

Figure 5.3


4 bit register l.jpg

4-Bit Register

Graphics from: Logic and Computer Design Fundamentals, Mano & Kime, Prentice Hall


4 bit register symbol l.jpg

4-Bit Register Symbol

Graphics from: Logic and Computer Design Fundamentals, Mano & Kime, Prentice Hall


4 bit register with parallel load l.jpg

4-Bit Register with Parallel Load

Note: When Load =0, the output is connected back to the input because the D-FF does not have a “no change” input condition

Graphics from: Logic and Computer Design Fundamentals, Mano & Kime, Prentice Hall


Shift registers l.jpg

Shift Registers

  • Logical shift

    Right or left

  • Arithmetic shift

    Right or left

  • Ring shift


Logical shift right l.jpg

0

R3

R2

R1

R0

Logical Shift Right

Examples:

0100 --> 0010

1110 --> 0111


Logical shift left l.jpg

0

R3

R2

R1

R0

Logical Shift Left

Examples:

0011 --> 0110

1101 --> 1010


Arithmetic shift right l.jpg

R3

R2

R1

R0

Arithmetic Shift Right

  • Examples:

  • Positive numbers 0100 --> 0010

    • same as logical shift

  • Negative numbers 1110 --> 1111

    • (-2) --> (-1) not same as logical shift


Arithmetic shift left l.jpg

0

R3

R2

R1

R0

Arithmetic Shift Left

  • Examples:

  • Positive numbers 0011 --> 0110

    • same as logical shift

  • Negative numbers 1101 --> 1010

    • (-3) --> (-6) same as logical shift


Ring shift right l.jpg

R3

R2

R1

R0

Ring Shift Right

Examples:

0101 --> 1010

1110 --> 0111


Mips shift instructions l.jpg

Shift a variable amount

Shift a fixed amount

MIPS Shift Instructions


4 bit shift register l.jpg

4-Bit Shift Register

  • On leading edge of clock pulse

  • Each FF gets output of previous

Graphics from: Logic and Computer Design Fundamentals, Mano & Kime, Prentice Hall


4 bit shift register symbol l.jpg

4-Bit Shift Register Symbol

Graphics from: Logic and Computer Design Fundamentals, Mano & Kime, Prentice Hall


Register block diagrams l.jpg

15

8

7

0

PC (H)

PC (L)

Register Block Diagrams

7 6 5 4 3 2 1 0

15

0

R2


Register language examples l.jpg

Register Language Examples

  • PC(L) or PC(7:0)

    Low order byte of register PC

  • PC(H) or PC(15:8)

    High order byte of register PC

  • R2 R1

    Transfer data from R1 to R2


Example register transfer l.jpg

Example Register Transfer

Transfer from R1 to R2 when K1 = 1

If (K1 = 1) then (R2  R1)

RTL Expression K1:R2  R2


Register transfers symbols l.jpg

Register Transfers Symbols


Arithmetic micro operations l.jpg

Arithmetic Micro-operations

R0  R1 + R2 Addition

R2  R21’s complement

R2  R2 + 12’s complement

R0  R1 +R2 +1Subtract

R1  R1 +1Increment

R1  R1 – 1Decrement


Logic micro operations l.jpg

Logic Micro-operations

R0  R1Logic NOT

R0  R1  R2Logic AND

R0  R1  R2Logic OR

R0  R1  R2Logic XOR

All Bitwise


Logic examples l.jpg

Logic Examples

AND or Mask operation


Logic examples32 l.jpg

Logic Examples

OR operation


Logic examples33 l.jpg

Logic Examples

EOR operation

Complements selected bits


Shift micro operations l.jpg

Shift Micro-operations

Before After

Shift leftR0  sl R00111000111100010

Shift right R0  sr R00111000100111000


Multiplexer based transfer l.jpg

Multiplexer-based Transfer

If (K1=1) then (R0  R1) else if (K2=1) then (R0  R2)

K1: R0  R1,K2: R0  R2


Detailed multiplexer select l.jpg

Detailed Multiplexer Select


Memory transfer l.jpg

Memory Transfer

Memory read:R0  M[AR]

Memory write: M[AR]  R0

M – Memory – typically RAM

AR – Address in memory


Serial adder l.jpg

Add B to A A

Serial Adder

  • When Shift = 0

    • C in = 1

  • When Shift = 1

    • C in = Clock

Figure 5-5 Page 229


Example serial add l.jpg

Example Serial Add


Shift register with parallel load l.jpg

0

0

Q

0

D

0

In

0

0

Q

D

In

Shift Load Operation

0 0 Nothing

0 1 Load parallel

1 X Shift

Shift Register with Parallel Load

0

0

0

1

0

X

Figure 5-6 Page 231


Shift register parallel load symbol l.jpg

Shift Register - Parallel Load Symbol

Graphics from: Logic and Computer Design Fundamentals, Mano & Kime, Prentice Hall


Bidirectional shift register one stage l.jpg

Bidirectional Shift Registerone stage

S1S2Operation

00NC

01Shift Dn

10Shift Up

11Par Load

S1S2 determine which line is connected to the D of Qi

Graphics from: Logic and Computer Design Fundamentals, Mano & Kime, Prentice Hall


Alu block diagram l.jpg

Register A

Register B

Add

Add/Subtract Unit

Sub

Accumulator

CCR

Condition Code Register

ALU Block Diagram

Normally, the accumulator has logical and arithmetic shift capability, both left and right


Transfer mechanisms l.jpg

Single Bus Example 7-6b

Transfer Mechanisms


Slide45 l.jpg

Note

Bidirectional

Enable

causes

output


Block diagram of a datapath l.jpg

B selects R3

Destination select

G to select A + B

A selects R2

Status bits

MD select

MF select

Block Diagram of a Datapath

Example

R1  R2 + R3

Figure 7-9

Page 328

Graphics from: Logic and Computer Design Fundamentals, Mano & Kime, Prentice Hall


Basics of fig 7 9 l.jpg

Basics of Fig 7-9

All registers connected to Mux A and Mux B

Mux B also has “constant in” select

Both Bus A & B have output paths

G selects arithmetic operation

H select shifting operation

Mux F selects output of ALU or shifter

Mux D selects what goes back to registers

Destination select chooses which register


Sequence of operations r1 r2 r3 l.jpg

Sequence of OperationsR1  R2 + R3

A select - R2 onto bus A

B select - R3 onto Mux B

Mux B select - R3 onto bus B

G select - operation of A + B

MF select - ALU out to Mux F in

MD select - Mux F out to Bus D

Destination select - Bus D to R1

Load enable - load R1


Block diagram of n bit alu l.jpg

Block Diagram of n-Bit ALU

Figure 7-10

Page 330

Graphics from: Logic and Computer Design Fundamentals, Mano & Kime, Prentice Hall


Diagram of arithmetic circuit l.jpg

0 Cin 1

00 G=A G=A+1

01 G=A+B G=A+B+1

10 G = A+B’ G=A+B’+1

11 G = A-1 G=A

Diagram of Arithmetic Circuit

Figure 7-11 Page 331

Graphics from: Logic and Computer Design Fundamentals, Mano & Kime, Prentice Hall


Block diagram of datapath l.jpg

Block Diagram of Datapath

Figure 7-9

Page 328

Graphics from: Logic and Computer Design Fundamentals, Mano & Kime, Prentice Hall


Alternative view of datapath fig 7 9 l.jpg

Alternative ViewofDatapathFig 7-9

Figure 7-19 Page 341


Micro operations l.jpg

Micro-operations

  • The elementary operations performed on the data stored in registers

  • Examples


Microinstruction format l.jpg

Microinstruction Format

Table 7-10 Page 342


Example microoperations l.jpg

Example Microoperations

Table7-11 Page 343


Examples binary control words l.jpg

Examples - Binary Control Words

Table 7-12 Page 344


Alternative control strategy l.jpg

Alternative Control Strategy

Figure 5.51


End of set 4 l.jpg

End of Set 4


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