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CoE - EE 00142 Computer Organization Set 4 Registers, Datapaths and OperationsPowerPoint Presentation

CoE - EE 00142 Computer Organization Set 4 Registers, Datapaths and Operations

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CoE - EE 00142 Computer Organization Set 4 Registers, Datapaths and Operations. Ron Hoelzeman. Datapaths & Control Units. Datapath Performs data-processing operations Control unit Determines the sequence of those operations. Control signals. ControlUnit. Status signals. Datapath.

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### CoE - EE 00142Computer OrganizationSet 4Registers, Datapaths and Operations

Ron Hoelzeman

Datapaths & Control Units

- Datapath
Performs data-processing operations

- Control unit
Determines the sequence of those operations

ControlUnit

Status signals

Datapath

Control inputs

Control outputs

Data inputs

Datapath - Control Unit InteractionData outputs

Signals

- Binary signals – one or zero
- Control signals
Activate data processing operations in proper sequence

- Status signals
Datapath feedback to control unit

Datapaths

- Best defined by registers and operations
- Examples:
Shift

Count

Load

clear

Register Transfer Operations

- Defined by:
The set of registers in the system

The operations performed on the data stored in the registers

The control that supervises the sequence of operations

Registers

- Flip Flops
Review of basics

- Registers
Loading

Shifting

Registers

- Used to store data or instructions
- Simply adjacent FF’s with loading and other control logic - gates
- Counters are a special case
- Sometimes use special names
accumulators, program counters, index registers, stack pointer, status register, etc.

Concept of Synchronization

Because of edge trigger, we can feed the output back around to the input

Figure 5.3

4-Bit Register

Graphics from: Logic and Computer Design Fundamentals, Mano & Kime, Prentice Hall

4-Bit Register Symbol

Graphics from: Logic and Computer Design Fundamentals, Mano & Kime, Prentice Hall

4-Bit Register with Parallel Load

Note: When Load =0, the output is connected back to the input because the D-FF does not have a “no change” input condition

Graphics from: Logic and Computer Design Fundamentals, Mano & Kime, Prentice Hall

Shift Registers

- Logical shift
Right or left

- Arithmetic shift
Right or left

- Ring shift

R3

R2

R1

R0

Arithmetic Shift Right- Examples:
- Positive numbers 0100 --> 0010
- same as logical shift

- Negative numbers 1110 --> 1111
- (-2) --> (-1) not same as logical shift

R3

R2

R1

R0

Arithmetic Shift Left- Examples:
- Positive numbers 0011 --> 0110
- same as logical shift

- Negative numbers 1101 --> 1010
- (-3) --> (-6) same as logical shift

4-Bit Shift Register

- On leading edge of clock pulse
- Each FF gets output of previous

Graphics from: Logic and Computer Design Fundamentals, Mano & Kime, Prentice Hall

4-Bit Shift Register Symbol

Graphics from: Logic and Computer Design Fundamentals, Mano & Kime, Prentice Hall

Register Language Examples

- PC(L) or PC(7:0)
Low order byte of register PC

- PC(H) or PC(15:8)
High order byte of register PC

- R2 R1
Transfer data from R1 to R2

Example Register Transfer

Transfer from R1 to R2 when K1 = 1

If (K1 = 1) then (R2 R1)

RTL Expression K1:R2 R2

Arithmetic Micro-operations

R0 R1 + R2 Addition

R2 R2 1’s complement

R2 R2 + 1 2’s complement

R0 R1 +R2 +1 Subtract

R1 R1 +1 Increment

R1 R1 – 1 Decrement

Logic Micro-operations

R0 R1 Logic NOT

R0 R1 R2 Logic AND

R0 R1 R2 Logic OR

R0 R1 R2 Logic XOR

All Bitwise

Logic Examples

AND or Mask operation

Logic Examples

OR operation

Shift Micro-operations

Before After

Shift left R0 sl R0 01110001 11100010

Shift right R0 sr R0 01110001 00111000

Multiplexer-based Transfer

If (K1=1) then (R0 R1) else if (K2=1) then (R0 R2)

K1: R0 R1,K2: R0 R2

Memory Transfer

Memory read: R0 M[AR]

Memory write: M[AR] R0

M – Memory – typically RAM

AR – Address in memory

0

Q

0

D

0

In

0

0

Q

D

In

Shift Load Operation

0 0 Nothing

0 1 Load parallel

1 X Shift

Shift Register with Parallel Load0

0

0

1

0

X

Figure 5-6 Page 231

Shift Register - Parallel Load Symbol

Graphics from: Logic and Computer Design Fundamentals, Mano & Kime, Prentice Hall

Bidirectional Shift Registerone stage

S1 S2 Operation

0 0 NC

0 1 Shift Dn

1 0 Shift Up

1 1 Par Load

S1S2 determine which line is connected to the D of Qi

Graphics from: Logic and Computer Design Fundamentals, Mano & Kime, Prentice Hall

Register B

Add

Add/Subtract Unit

Sub

Accumulator

CCR

Condition Code Register

ALU Block DiagramNormally, the accumulator has logical and arithmetic shift capability, both left and right

Transfer Mechanisms

Destination select

G to select A + B

A selects R2

Status bits

MD select

MF select

Block Diagram of a DatapathExample

R1 R2 + R3

Figure 7-9

Page 328

Graphics from: Logic and Computer Design Fundamentals, Mano & Kime, Prentice Hall

Basics of Fig 7-9

All registers connected to Mux A and Mux B

Mux B also has “constant in” select

Both Bus A & B have output paths

G selects arithmetic operation

H select shifting operation

Mux F selects output of ALU or shifter

Mux D selects what goes back to registers

Destination select chooses which register

Sequence of OperationsR1 R2 + R3

A select - R2 onto bus A

B select - R3 onto Mux B

Mux B select - R3 onto bus B

G select - operation of A + B

MF select - ALU out to Mux F in

MD select - Mux F out to Bus D

Destination select - Bus D to R1

Load enable - load R1

Block Diagram of n-Bit ALU

Figure 7-10

Page 330

Graphics from: Logic and Computer Design Fundamentals, Mano & Kime, Prentice Hall

0 Cin 1

00 G=A G=A+1

01 G=A+B G=A+B+1

10 G = A+B’ G=A+B’+1

11 G = A-1 G=A

Diagram of Arithmetic CircuitFigure 7-11 Page 331

Graphics from: Logic and Computer Design Fundamentals, Mano & Kime, Prentice Hall

Block Diagram of Datapath

Figure 7-9

Page 328

Graphics from: Logic and Computer Design Fundamentals, Mano & Kime, Prentice Hall

Alternative ViewofDatapathFig 7-9

Figure 7-19 Page 341

Micro-operations

- The elementary operations performed on the data stored in registers
- Examples

Microinstruction Format

Table 7-10 Page 342

Example Microoperations

Table7-11 Page 343

Examples - Binary Control Words

Table 7-12 Page 344

Alternative Control Strategy

Figure 5.51

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