coe ee 00142 computer organization set 4 registers datapaths and operations
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CoE - EE 00142 Computer Organization Set 4 Registers, Datapaths and Operations. Ron Hoelzeman. Datapaths & Control Units. Datapath Performs data-processing operations Control unit Determines the sequence of those operations. Control signals. ControlUnit. Status signals. Datapath.

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datapaths control units
Datapaths & Control Units
  • Datapath

Performs data-processing operations

  • Control unit

Determines the sequence of those operations

datapath control unit interaction

Control signals

ControlUnit

Status signals

Datapath

Control inputs

Control outputs

Data inputs

Datapath - Control Unit Interaction

Data outputs

signals
Signals
  • Binary signals – one or zero
  • Control signals

Activate data processing operations in proper sequence

  • Status signals

Datapath feedback to control unit

datapaths
Datapaths
  • Best defined by registers and operations
  • Examples:

Shift

Count

Load

clear

register transfer operations
Register Transfer Operations
  • Defined by:

The set of registers in the system

The operations performed on the data stored in the registers

The control that supervises the sequence of operations

registers
Registers
  • Flip Flops

Review of basics

  • Registers

Loading

Shifting

registers8
Registers
  • Used to store data or instructions
  • Simply adjacent FF’s with loading and other control logic - gates
  • Counters are a special case
  • Sometimes use special names

accumulators, program counters, index registers, stack pointer, status register, etc.

register

R3

R2

R1

R0

R3

R2

R1

R0

Register

Remember - just a bundle of Flip-Flops

d latch or flip flop

Input

Output

Clock

D Latch or Flip Flop

Triggers on positive edge of clock pulse

concept of synchronization
Concept of Synchronization

Triggers on positive edge of clock pulse

Figure 5.2

concept of synchronization12
Concept of Synchronization

Because of edge trigger, we can feed the output back around to the input

Figure 5.3

4 bit register
4-Bit Register

Graphics from: Logic and Computer Design Fundamentals, Mano & Kime, Prentice Hall

4 bit register symbol
4-Bit Register Symbol

Graphics from: Logic and Computer Design Fundamentals, Mano & Kime, Prentice Hall

4 bit register with parallel load
4-Bit Register with Parallel Load

Note: When Load =0, the output is connected back to the input because the D-FF does not have a “no change” input condition

Graphics from: Logic and Computer Design Fundamentals, Mano & Kime, Prentice Hall

shift registers
Shift Registers
  • Logical shift

Right or left

  • Arithmetic shift

Right or left

  • Ring shift
logical shift right

0

R3

R2

R1

R0

Logical Shift Right

Examples:

0100 --> 0010

1110 --> 0111

logical shift left

0

R3

R2

R1

R0

Logical Shift Left

Examples:

0011 --> 0110

1101 --> 1010

arithmetic shift right

R3

R2

R1

R0

Arithmetic Shift Right
  • Examples:
  • Positive numbers 0100 --> 0010
    • same as logical shift
  • Negative numbers 1110 --> 1111
    • (-2) --> (-1) not same as logical shift
arithmetic shift left

0

R3

R2

R1

R0

Arithmetic Shift Left
  • Examples:
  • Positive numbers 0011 --> 0110
    • same as logical shift
  • Negative numbers 1101 --> 1010
    • (-3) --> (-6) same as logical shift
ring shift right

R3

R2

R1

R0

Ring Shift Right

Examples:

0101 --> 1010

1110 --> 0111

4 bit shift register
4-Bit Shift Register
  • On leading edge of clock pulse
  • Each FF gets output of previous

Graphics from: Logic and Computer Design Fundamentals, Mano & Kime, Prentice Hall

4 bit shift register symbol
4-Bit Shift Register Symbol

Graphics from: Logic and Computer Design Fundamentals, Mano & Kime, Prentice Hall

register block diagrams

15

8

7

0

PC (H)

PC (L)

Register Block Diagrams

7 6 5 4 3 2 1 0

15

0

R2

register language examples
Register Language Examples
  • PC(L) or PC(7:0)

Low order byte of register PC

  • PC(H) or PC(15:8)

High order byte of register PC

  • R2 R1

Transfer data from R1 to R2

example register transfer
Example Register Transfer

Transfer from R1 to R2 when K1 = 1

If (K1 = 1) then (R2  R1)

RTL Expression K1:R2  R2

arithmetic micro operations
Arithmetic Micro-operations

R0  R1 + R2 Addition

R2  R2 1’s complement

R2  R2 + 1 2’s complement

R0  R1 +R2 +1 Subtract

R1  R1 +1 Increment

R1  R1 – 1 Decrement

logic micro operations
Logic Micro-operations

R0  R1 Logic NOT

R0  R1  R2 Logic AND

R0  R1  R2 Logic OR

R0  R1  R2 Logic XOR

All Bitwise

logic examples
Logic Examples

AND or Mask operation

logic examples32
Logic Examples

OR operation

logic examples33
Logic Examples

EOR operation

Complements selected bits

shift micro operations
Shift Micro-operations

Before After

Shift left R0  sl R0 01110001 11100010

Shift right R0  sr R0 01110001 00111000

multiplexer based transfer
Multiplexer-based Transfer

If (K1=1) then (R0  R1) else if (K2=1) then (R0  R2)

K1: R0  R1,K2: R0  R2

memory transfer
Memory Transfer

Memory read: R0  M[AR]

Memory write: M[AR]  R0

M – Memory – typically RAM

AR – Address in memory

serial adder

Add B to A A

Serial Adder
  • When Shift = 0
    • C in = 1
  • When Shift = 1
    • C in = Clock

Figure 5-5 Page 229

shift register with parallel load

0

0

Q

0

D

0

In

0

0

Q

D

In

Shift Load Operation

0 0 Nothing

0 1 Load parallel

1 X Shift

Shift Register with Parallel Load

0

0

0

1

0

X

Figure 5-6 Page 231

shift register parallel load symbol
Shift Register - Parallel Load Symbol

Graphics from: Logic and Computer Design Fundamentals, Mano & Kime, Prentice Hall

bidirectional shift register one stage
Bidirectional Shift Registerone stage

S1 S2 Operation

0 0 NC

0 1 Shift Dn

1 0 Shift Up

1 1 Par Load

S1S2 determine which line is connected to the D of Qi

Graphics from: Logic and Computer Design Fundamentals, Mano & Kime, Prentice Hall

alu block diagram

Register A

Register B

Add

Add/Subtract Unit

Sub

Accumulator

CCR

Condition Code Register

ALU Block Diagram

Normally, the accumulator has logical and arithmetic shift capability, both left and right

slide45

Note

Bidirectional

Enable

causes

output

block diagram of a datapath

B selects R3

Destination select

G to select A + B

A selects R2

Status bits

MD select

MF select

Block Diagram of a Datapath

Example

R1  R2 + R3

Figure 7-9

Page 328

Graphics from: Logic and Computer Design Fundamentals, Mano & Kime, Prentice Hall

basics of fig 7 9
Basics of Fig 7-9

All registers connected to Mux A and Mux B

Mux B also has “constant in” select

Both Bus A & B have output paths

G selects arithmetic operation

H select shifting operation

Mux F selects output of ALU or shifter

Mux D selects what goes back to registers

Destination select chooses which register

sequence of operations r1 r2 r3
Sequence of OperationsR1  R2 + R3

A select - R2 onto bus A

B select - R3 onto Mux B

Mux B select - R3 onto bus B

G select - operation of A + B

MF select - ALU out to Mux F in

MD select - Mux F out to Bus D

Destination select - Bus D to R1

Load enable - load R1

block diagram of n bit alu
Block Diagram of n-Bit ALU

Figure 7-10

Page 330

Graphics from: Logic and Computer Design Fundamentals, Mano & Kime, Prentice Hall

diagram of arithmetic circuit

0 Cin 1

00 G=A G=A+1

01 G=A+B G=A+B+1

10 G = A+B’ G=A+B’+1

11 G = A-1 G=A

Diagram of Arithmetic Circuit

Figure 7-11 Page 331

Graphics from: Logic and Computer Design Fundamentals, Mano & Kime, Prentice Hall

block diagram of datapath
Block Diagram of Datapath

Figure 7-9

Page 328

Graphics from: Logic and Computer Design Fundamentals, Mano & Kime, Prentice Hall

micro operations
Micro-operations
  • The elementary operations performed on the data stored in registers
  • Examples
microinstruction format
Microinstruction Format

Table 7-10 Page 342

example microoperations
Example Microoperations

Table7-11 Page 343

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