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PC Architectures: PC History . What’s a PC? A “PC” is a personal computer, but not every personal computer is a “PC” (e.g. Apple Mac) PC used to be “IBM-compatible”. PC Architectures: PC History . How come IBM’s PCs became a standard? PC IP (Intellectual Property):

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PC Architectures: PC History

  • What’s a PC?

    • A “PC” is a personal computer, but not every personal computer is a “PC” (e.g. Apple Mac)

    • PC used to be “IBM-compatible”

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PC Architectures: PC History

  • How come IBM’s PCs became a standard?

    • PC IP (Intellectual Property):

      • HW can only be protected through patents

        • PC based on standard components (8088, 8259, etc), and as such was not wholly patentable.

        • Anyone could easily copy PC hardware

      • SW (protected through copyrights)

        • BIOS:Originally written and owned by IBM. Reverse-engineered by Phoenix. Also available from AMI, Microid, etc.

        • DOS:IBM hired Microsoft to develop DOS. IBM failed to secure exclusive rights (“most costly business mistake in history”). Microsoft licensed DOS to PC cloners like Compaq, etc.

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PC Architectures: PC History

  • Who controls the PC standard today?

    • Who controls PC Software?MICROSOFT(Provides OS bundled with lots of SW. Applications)

    • Who controls PC Hardware?INTEL(No 1 manufacturer of processors, chipsets, motherboards)80% of all PC systems are based on Intel motherboards!

    • PCs are often called WINTEL systems...

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PC Architectures: PC History

  • A few PC History Milestones

    • 1971: Intel introduces 4004 processor

    • 1975: Altair 8800 (first commercial personal computer)

    • 1976: Apple I (sold for $666)

    • 1977: Apple II. Tandy TRS-80. Commodore PET.

    • 1978: Intel introduces 8086

    • 1979: Motorola introduces 68000

    • 1980: Seagate introduces first hard disk drive

    • 1981: IBM releases its first PC

    • 1984: Apple Macintosh. IBM PC AT.

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PC Architectures: PC History

  • Why have PCs been so successful?

    • open standardised architecture

    • expandable hardware(ports and expansion slots: ISA, PCI, PC-Card…)

    • multitude of hardware manufacturers(cost, performance, choice)

    • compatibility (between, and backwards)

    • (few) standardised operating systems

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PC Architectures: PC History

  • Todays PCs are backward-compatible with the original IBM PC design

  • Supporting legacy code

    • is important element of the success of the PC Architecture

    • places restrictions on PC designs

  • Current trend is to discontinue legacy systems (such as ISA bus) which are no longer required

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Early PCs

  • IBM PC (1981):

    • i8088 based, 4.77 MHz, 8-bit PC-bus,No hard disk – one or two floppies.

  • IBM PC/XT (1983):

    • Included a 10MB Hard Disk, and a better floppy 

    • Many PC and PC/XT Clones used the i8086

  • IBM PC/AT (1984):

    • i80286 based

    • 6 MHz (first release)

    • 16-bit AT-bus (which later became the ISA Standard)

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IBM PC Brief History: Family Two Systems

Industry ignored MicroChannel & developed EISA

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PC/XT & PC/AT

We will look at the following elements of the early PC architectures:

  • PC/AT or ISA Bus Standard

  • Interrupt Handling

  • DMA Handling

  • Serial (COM) Port

  • Parallel (LPT) Port

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PC/AT Support Circuitry

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PC/AT Block Diagram

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PC/AT Bus Standards

  • The AT-Bus is a 16-bit (data) bus and is based on the 8-bit PC-Bus

  • The ISA (Industry Standard Architecture) standard formalised the AT-Bus (16-bit) standard as an industry standard, and this standard is commonly referred to as the 'ISA Bus' standard

  • A more advanced bus, the EISA bus (Enhanced Industry Standard Architecture) is a standard, which is upwards compatible to the ISA bus

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PC Bus (8-bit)

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ISA Bus Connector

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Multiple Interrupt Sources in the PC

  • A PC processor can receive interrupt requests form more than one source

  • System has to resolve two things:

  • Identify what device requested the interrupt

  • Prioritise Interrupts when two requests happen at the same time.

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Vectored Interrupts

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Priority Schemes

  • A priority encoder is used to prioritise interrupts, e.g.

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Interrupts on the PC

  • PC uses i8259a Programmable Interrupt Controller: ancestor of APIC

Note that this is an 8-bit device

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i8259A Block Diagram

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i8259A Interrupt Timing

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i8259a in the PC

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Cascading i8259As in the PC/AT

The interrupt request signal of the slave 8259 is connected to IRQ2 of the master 8259. The master passes control signals to the slave via the connections CAS0..CAS2.

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PC/AT Interrupt Priorities

Priority Use of PC/AT Interrupt

Highest IRQ0 Timer 0

IRQ1 Keyboard

IRQ2 From slave 8259 

IRQ8 Real time clock

IRQ9 *

IRQ10

IRQ11

IRQ12

IRQ13 C0-processor

IRQ14 Hard disk controller

IRQ15

IRQ3 COM2 port

IRQ4 COM1 port

IRQ5 LPT2

IRQ6 Floppydisk controller

Lowest IRQ7 LPT1  

* IRQ9 interrupt is redirected to IRQ2 vector

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PC/AT Interrupt Vectors

  • I80x86: the interrupt vector table is at the bottom of the memory map

  • The table is 1024 (400h) bytes in size and can contain 256 vectors. Each vector location is 4 bytes long (segment:offset address)

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PC/AT interrupt sources

  • An interrupt can be triggered by:

    • Software (also called Exceptions)

      • Execution of INT instruction

      • some other internal event (e.g. division error)  

    • Hardware

      • Peripheral devices usually generate external interrupt requests as asynchronous events.

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PC/AT Hardware Interrupt

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PC/AT Hardware Interrupt(2)

  • The vector pointer is transmitted from the i8259A to the MPU on the second INTA pulse of the interrupt cycle:

  • Vector Pointer: A9 A8 A7 A6 A5 L3 L2 L1

  • A9..A5: locates the position of the 32 byte area within the vector table. Each i8259 has a 32 byte area to hold the eight 4-byte vector addresses 

  • L3..L1: interrupt level (1 of 8) from the 8259 

  • The processor multiplies the vector pointer by 4 to form a 10-bit address

  • This is the starting byte of the vector 4 byte location.

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PC/AT Interrupt Vector Table

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Software Interrupts triggered from a program – INT X

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Direct Memory Access: DMA

  • DMA provides direct access to the memory while the processor is temporarily disabled

  • Allows data to be transferred between memory and I/O devices at a rate that is limited only by the speed of the memory components or I/O components

  • DMA used for e.g.:

    • Memory refresh (Dynamic RAM)

    • Magnetic/optical read/write operations

    • Video operations (e.g. screen refresh)

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Direct Memory Access: DMA

  • DMA Definitions

    • DMA ReadTransfers data from memory to I/O

    • DMA WriteTransfers data from I/O to memory

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DMA: i8237A

  • DMA Controller: i8237A

  • i8238A = special purpose microcontroller for high-speed data transfer between memory and I/O

  • Although i8237A may not appear as a discrete component in recent PCs, it’s still there… (integrated in chipsets, ISPC)

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DMA in the PC & PC/AT: i8237A

  • The i8237A has four independent DMA channels

  • Original PC/XT design had one i8237A for four DMA channels

  • PC/AT used two i8237As to provide 7 DMA channels

  • i8237A is programmable device and can be configured for single transfers, block transfers, Reads, Writes or Memory-to-Memory transfers 

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i8237A

  • i8237A allows byte addressing for 8-bit data transfers

  • In the PC/AT design, a contrived 16-bit transfer design is implemented using the i8237A 

  • i8237A uses a multiplexed address and data bus to reduce the device pin count.

    • DB0..DB7 lines contain the data bus along with the high byte of the 16-bit address bus.

    • An external latch is required to demultiplex the address lines

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i8237A Logic symbol

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i8237A Block Diagram

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DMA Address Tracking

  • The i8237A has four registers for tracking memory addresses during a DMA block

  • BASE ADDRESS REGISTER

  • BASE WORD COUNT REGISTER

  • CURRENT ADDRESS REGISTER

  • CURRENT WORD COUNT REGISTER

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DMA in the PC/XT

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Cascaded i8237As in the PC/AT

DMA Cascadation

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PC/AT DMA Channel priorities

  • DMA channel 0 (DREQ0) has the highest priority

  • DMA channel 7 (DREQ7) has the lowest

  • Note, when a DMA transfer is in session, it cannot be 'interrupted' by another DMA request, even if the DMA request is made by a higher priority DMA channel.

  • The current DMA transfer session will be completed before the pending DMA request is accepted

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DMA Channels in the PC/AT

DMA Priority Pre-defined 8-bit or

Use in PC/AT 16-bit

____________________________________________________________

DREQ0 Highest Memory Refresh* 8-bits

DREQ1 Not defined 8-bits

DREQ2 Floppy Disk 8-bits

DREQ3 Not defined 8-bits

DREQ4 Cascade not used

DREQ5 Not defined 16-bits

DREQ6 Not defined 16-bits

DREQ7 Lowest Not defined 16-bits

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PC/AT Parallel Port (1)

  • The parallel printer port on the PC/AT is referred to as an LPT (Line Printer)

  • Originally designed to support theCentronics parallel printer interface standard

  • The LPT port is often used to connect to a range of devices e.g. Dongle, A/D converter, D/A converter 

  • PC/AT typically allows up to four ports: LPT1 - LPT4

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I/O addresses for LPT1 and LPT2

LPT1 LPT2

Data latch output 8 bits 378h 278h

Data Latch

read back (verify) 8 bits 378h* 278h*

Printer controls

output latch 4 bits+Int 37Ah 27Ah

Printer controls

latch read back 4 bits+Int 37Ah** 27Ah**

Printer status

read 5 bits 379h 279h

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PC/AT Parallel Port (3)

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PC/AT Parallel Port (4)

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Parallel Port Enhancements

The parallel port is highly non-standard

These are some attempts to standardise & enhance the parallel port:

  • Enhanced Parallel Port (EPP)

    • This is an Intel defined specification, also called fast Mode Parallel Port

  • Enhanced Compatibility Port (ECP)

    • Similar to EPP

  • The IEEE 1284 Standard

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PC/AT Serial Port (1)

  • The PC/AT serial port is a programmable full-duplex asynchronous communications communication channel, based upon the EIA, RS-232-C communication's standard 

  • The RS-232-C standard defines a 25-way D-type physical connector

  • IBM implemented a sub-set of this standard and defined a 9-pin D-type connector

  • IBM 9-pin interface is now the 'de-facto' standard for implementation of a limited serial, asynchronous communications port

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PC/AT Serial Port (2)

9 Pin Conn 25 Pin Conn Signal Name

1 8 DCD (data carrier detect)

  2 3 RX Data (receive data)

  3 2 TX Data (transmit data)

  4 20 DTR (data terminal ready)

  5 7 GND (signal ground)

  6 6 DSR (data set ready)

  7 4 RTS (request to send)

  8 5 CTS (clear to send)

9 22 RI (ring indicator)

 Shell 1, Shell FG (frame ground)

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PC/AT Serial Port

  • Asynchronous. Need of framing… Start Bit

  • Optional parity bit. 1-2 stop bits.

  • Bitrates: 50Bd..19.2kBd (PC/XT and PC/AT)..115.2kBd

  • RS232 Levels: 3..15V Mark (logic 0). –3..-15V Space (logic 1)

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COM1 Port

PC/AT Serial Port

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THE PC/AT KEYBOARD CONTROLLER AND INTERFACE

  • PC/AT keyboard had 102 keys

  • Keyboard had its own small microcontroller (typically 8049)

  • 8049 had its own ROM (2Kbytes), RAM and I/O ports

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Keyboard circuit

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PC/AT Keyboard Interface

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PC/AT I/O Mapping

Hex Range Device

___________________________________________________

000 - 01F DMA controller 1, i8237A

020 - 03F Interrupt controller 1, i8259, master

040 - 05F Timer, i8253/i8254

060 - 06F 8042 Keyboard controller

070 - 07F Real-time clock, NMI mask

080 - 09F DMA registers

0A0 - 0BF Interrupt controller 2, i8259A, slave

0C0 - 0DF DMA controller 2, i8237A

0F0 Clear math coprocessor busy

0F1 Reset math coprocessor

0F8 - 0FF Math coprocessor

1F0 - 1F8 Fixed disk

200 - 207 Game 1/0

278 - 27F Parallel printer port 2 (LPT 2)

2F8 - 2FF Serial port 2, (COM 2 )

300 - 31F Prototype card

360 - 36F Reserved

378 - 37F Parallel printer port 1 (LPT 1)

380 - 38F SDLC, bisynchronous 2

3A0 - 3AF Bisynchronous 1

3B0 - 3BF Monochrome display/printer adapter

3C0 - 3CF Reserved

3D0 - 3DF Colour/graphics monitor adapter

3F0 - 3F7 Diskette controller

3F8 - 3FF Serial port 1 (COM 1)

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