Introduction to Parallel Processing Ch. 12, Pg. 514526. CS147 Louis Huie. Topics Covered. An Overview of Parallel Processing Parallelism in Uniprocessor Systems Organization of Multiprocessor Flynn’s Classification System Topologies MIMD System Architectures.
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The task of ordering a shuffled deck of cards by suit and then by rank can be done faster if the task is carried out by two or more people. By splitting up the decks and performing the instructions simultaneously, then at the end combining the partial solutions you have performed parallel processing.
Another analogy is having several students grade quizzes simultaneously. Quizzes are distributed to a few students and different problems are graded by each student at the same time. After they are completed, the graded quizzes are then gathered and the scores are recorded.
Each stage of a reconfigurable arithmetic pipeline has a multiplexer at its input. The multiplexer may pass input data, or the data output from other stages, to the stage inputs. The control unit of the CPU sets the select signals of the multiplexer to control the flow of data, thus configuring the pipeline.
To
memory
and
registers
0
1
MUX
2
3
S1 S0
*
LATCH
0
1
MUX
2
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S1 S0

LATCH
0
1
MUX
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S1 S0
+
LATCH
0
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MUX
2
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S1 S0
Data Inputs
0 0
x x
0 1
1 1
Although arithmetic pipelines can perform many iterations of the same operation in parallel, they cannot perform different operations simultaneously. To perform different arithmetic operations in parallel, a CPU may include a vectored arithmetic unit.
A vector arithmetic unit contains multiple functional units that perform addition, subtraction, and other functions. The control unit routes input values to the different functional units to allow the CPU to execute multiple instructions simultaneously.
For the operations AB+C and DEF, the CPU would route B and C to an adder and then route E and F to a subtractor for simultaneous execution.
Data
Input
Connections
Data
Input
Connections
+

Data
Inputs
*
%
AB+C
DEF
Simple Diagrammatic Representation
4 categories of Flynn’s classification of multiprocessor systems by their instruction and data streams
Simple Diagrammatic Representation
Simple Diagrammatic Representation
Simple Diagrammatic Representation
(Shared Memory)
Simple Diagrammatic Representation(DistributedMemory)
Topologies
Shared Bus Topology the same operation in parallel, they cannot perform different operations simultaneously. To perform different arithmetic operations in parallel, a CPU may include a vectored arithmetic unit.
Processors communicate with each other via a single bus that can only handle one data transmissions at a time.
In most shared buses, processors directly communicate with their own local memory.
System Topologies
M
M
M
P
P
P
Shared Bus
Global
memory
Ring Topology the same operation in parallel, they cannot perform different operations simultaneously. To perform different arithmetic operations in parallel, a CPU may include a vectored arithmetic unit.
Uses direct connections between processors instead of a shared bus.
Allows communication links to be active simultaneously but data may have to travel through several processors to reach its destination.
System TopologiesP
P
P
P
P
P
Tree Topology the same operation in parallel, they cannot perform different operations simultaneously. To perform different arithmetic operations in parallel, a CPU may include a vectored arithmetic unit.
Uses direct connections between processors; each having three connections.
There is only one unique path between any pair of processors.
System TopologiesP
P
P
P
P
P
P
Mesh Topology the same operation in parallel, they cannot perform different operations simultaneously. To perform different arithmetic operations in parallel, a CPU may include a vectored arithmetic unit.
In the mesh topology, every processor connects to the processors above and below it, and to its right and left.
Systems TopologiesP
P
P
P
P
P
P
P
P
Hypercube Topology the same operation in parallel, they cannot perform different operations simultaneously. To perform different arithmetic operations in parallel, a CPU may include a vectored arithmetic unit.
Is a multiple mesh topology.
Each processor connects to all other processors whose binary values differ by one bit. For example, processor 0(0000) connects to 1(0001) or 2(0010).
System TopologiesP
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
Completely Connected Topology the same operation in parallel, they cannot perform different operations simultaneously. To perform different arithmetic operations in parallel, a CPU may include a vectored arithmetic unit.
Every processor has
n1 connections, one to each of the other processors.
There is an increase in complexity as the system grows but this offers maximum communication capabilities.
System TopologiesP
P
P
P
P
P
P
P
Processor 1
Communications
mechanism
Processor 2
Shared
Memory
Processor n
Processor 1
Processor 2
Processor n
Memory 1
Memory 2
Memory n
Communications mechanism