All the chips outside… and around the PC what new platforms? Apps? Challenges, what’s interesting, and what needs doing?. Gordon Bell Bay Area Research Center Microsoft Corporation.
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All the chips outside… and around the PCwhat new platforms? Apps?Challenges, what’s interesting, and what needs doing?
Bay Area Research Center
Architecture changes when everyone and everything is mobile!Power, security, RF, WWW, display, data-types e.g. video & voice… it’s the application of architecture!
Non-PCdevices and Internet
It needs to continue to be upward. These scalable systems provide the highest technical (Flops) and commercial (TPC) performance.
They drive microprocessor competition!
The Dawn Of The PC-Plus Era, Not The Post-PC Era…devices aggregate via PCs!!!
Automation & Security
C = Commercial; C’ = Consumer
A 60+ year view
VtubesTrans.MSI(mini) Micro RISCnMicr
(single execution stream)
Parallel programs aka Cluster Computing <---------------
multicomputers <--MPP era------
ultracomputers 10X in size & price!10x MPP
“in situ” resources 100x in //sm NOWVLSCC
WAN/LAN SAN DSM SM
WAN/LAN SAN DSM SM
Evans and Sutherland Computer
Floating Point Systems
Goodyear Aerospace MPP
Intel Scientific Computers
International Parallel Machines
Kendall Square Research
Key Computer Laboratories
Scientific Computer Systems (SCS)
To cluster or not to cluster… don’t we need a single, shared memory?
General purpose, non-parallelizable codes(PCs have it!)
Vectorizable & //able(Supers & small DSMs)
Hand tuned, one-ofMPP course grainMPP embarrassingly //(Clusters of PCs...)
If central control & rich then IBM or large SMPs
else PC Clusters
servers & terms
servers & terminals
Wide & Local
built from PCs
A space, time (bandwidth), & generation scalable environment
uni- & mP servers
(UNIX & NT)
servers buit from
(CATV or ATM
Petaflops study target
Top two Compaq systems are:1.1 & 1.5X faster than IBM SPs;1/3 price of IBM1/5 price of SUN
Courtesy of Dr. Thomas Sterling, Caltech
Size scalable -- designed from a few components, with no bottlenecks
Generation scaling -- no rewrite/recompile or user effort to run across generations of an architecture
Reliability scaling… chose any level
Geographic scaling -- compute anywhere (e.g. multiple sites or in situ workstation sites)
Problem x machine scalability -- ability of an algorithm or program to exist at a range of sizes that run efficiently on a given, scalable computer.
Problem x machine space => run time: problem scale, machine scale (#p), run time, implies speedup and efficiency,
1st & 2nd Lvl Caches
Two results per clock
Two results per clock
(Will be 4 in next Gen SGI)
Vector lengths arbitrary
Vector lengths fixed
Vectors fed at low speed
Vectors fed at high speed
Cache based systems are nothing more than “vector” processors with a highly programmable “vector” register set (the caches). These caches are 1000x larger than the vector registers on a Cray vector system, and provide the opportunity to execute vector work at a very high sustained rate. In particular, note 512 CPU Origins contain 4 GBytes of cache. This is larger than most problems of interest, and offers a tremendous opportunity for high performance across a large number of CPUs. This has been borne out in fact at NASA Ames.
to be the main line
Mp — S — Pc
: | :
|—————— S.fc — Ms
|— S.WAN —
MpPcMs — S.Lan/Cluster/Wan — :
The 500GB disc card
An array of discs
Can be used as
1 striped disc
50 FT discs
LOTS of accesses/second
A few disks are replaced by 10s of Gbytes of RAM and a processor to run Apps!!
single-thread single-stream tcp/ip via 7 hops desktop-to-desktop …Win 2K out of the box performance*
San Francisco, CA
Performance in Mflop/s
Die (sq. in.)188.8.131.52x
Performance Gap:(grows 50% / year)
*Processors, Memory, Communication & Memory Links,
UMS : VLSI = microprocessor : special systemsSoftware : Hardware