Multiplication and division algorithms
Download
1 / 24

MULTIPLICATION AND DIVISION ALGORITHMS - PowerPoint PPT Presentation


  • 178 Views
  • Uploaded on

MULTIPLICATION AND DIVISION ALGORITHMS. Presented by: Manpreet Bhullar & Matt Hattersley. Instructor: Prof. Ten Eyck Course: Computer Architecture (CMSC 415). Binary Multiplication. 147 10010011 Multiplicand * 85 * 01010101 Multiplier 10010011 00000000

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about 'MULTIPLICATION AND DIVISION ALGORITHMS' - Olivia


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
Multiplication and division algorithms

MULTIPLICATION AND DIVISION ALGORITHMS

Presented by:

Manpreet Bhullar & Matt Hattersley

Instructor: Prof. Ten Eyck

Course: Computer Architecture

(CMSC 415)


Binary multiplication
Binary Multiplication

147 10010011 Multiplicand

* 85* 01010101 Multiplier

10010011

00000000

10010011

00000000

10010011

00000000

10010011

00000000

12495 011000011001111 Product

Computer Architecture Project


Multiply Algorithm Version 1

Multiplier0 = 0

Multiplier0 = 1

1. Test

Multiplier0

1a. Add multiplicand to product &

place the result in Product register

2. Shift the M’cand register left 1 bit

3. Shift the M’plier register right 1 bit

64th

repetition?

No: < 64 repetitions

Yes: 64 repetitions

Done

Computer Architecture Project


Multiplication hardware 1
Multiplication Hardware 1

Shift_left

32-bit multiplicand

64 bits

Shift_right

16-bit multiplier

32-bit ALU

16 bits

lsb

Write

32-bit product

Control

32 bits

Computer Architecture Project


Multiplication hardware
Multiplication Hardware

  • Product: initialized to all 0’s

  • Control: decides when to shift the Multiplier and Multiplicand registers and when to write new values to Product register

  • At the end, the multiplier is out of the product register and the product contains the result

Computer Architecture Project


Step by step transition in the registers during the multiplication process 1
Step-by-step transition in the registers during the multiplication process 1

For Version 1:

Computer Architecture Project


Thinking about new algorithm
Thinking about new algorithm… multiplication process 1

Changes can be made:

  • -instead of shifting multiplicand left, shift product right

  • -adder can be shortened to length of the multiplier & multiplicand(8 bits in our example)

  • -place multiplier in right half of the product register(multiplier will disappear as product is shifted right

  • -add multiplicand to left half of product

Computer Architecture Project


Multiply algorithm final version
Multiply Algorithm Final multiplication process 1Version

Product = 0

Product = 1

1. Test

Product00

1a. Add multiplicand to the left half ofproduct &

place the result in the left half ofProduct register

2. Shift the Product register right 1 bit.

64th

repetition?

No: < 64 repetitions

Yes: 64 repetitions

Done

Computer Architecture Project


Step by step transition in the registers during the multiplication process final
Step-by-step transition in the registers during the multiplication process (Final)

For FinalVersion :

Computer Architecture Project


Multiplication Hardware(Final) multiplication process (Final)

Shift_left

multiplicand

16 bits

16-bit ALU

Write

product

Control Test

32 bits

Shift_right

Computer Architecture Project


Multiply in mips
Multiply in MIPS multiplication process (Final)

  • Can multiply variable by any constant using MIPS sll and add instructions: i' = i * 10; /* assume i: $s0 */ sll $t0, $s0, 3 # i * 23 add $t1, $zero, $t0 sll $t0, $s0, 1 # i * 21add $s0, $t1, $t0

  • MIPS multiply instructions: mult, multu

  • mult $t0, $t1

    • puts 64-bit product in pair of new registers hi, lo; copy to $n by mfhi, mflo

    • 32-bit integer result in register lo

Computer Architecture Project


Multiplying signed numbers
Multiplying Signed numbers multiplication process (Final)

  • Main difficulty arises when signed numbers are involved.

  • Naive approach: convert both operands to positive numbers,

  • multiply, then calculate separately the sign of the

  • product and convert if necessary.

  • A better approach: Booth’s Algorithm.

  • Booth’s idea: if during the scan of the multiplier, we observe a

  • sequence of 1’s, we can replace it first by subtracting the multiplicand

  • (instead of adding it to the product) and later, add the multiplicand,

  • after seeing the last 1 of the sequence.

Computer Architecture Project


For Example: multiplication process (Final)

0110 x 0011 (6x3) This can be done by (8- 2) x3 as well, or (1000 - 0010) x 0011(using 8 bit words)

At start, product = 00000000, looking at each bit of the multiplier 0110, from right to left:

0: product unchanged: 00000000 ,

shift multiplicand left: 00110

1: start of a sequence:

subtract multiplicand from product: 00000000 - 00110 = 11111010 ,

shift multiplicand left: 001100

1: middle of sequence, product unchanged: 11111010,

shift multiplicand left: 0011000

0: end of sequence:

add multiplicand to product: 11111010 + 0011000 = 00010010 = 18

shift multiplicand left: 00110000

Computer Architecture Project


Booth s algorithm
Booth’s Algorithm multiplication process (Final)

  • Scan the multiplier from right to left, observing, at each step, both the current bit and the previous bit:

  • Depending on (current, previous) bits:

  • 00 : Middle of a string of 0’s: do no arithmetic operation.

  • 10 : Beginning of a string of 1’s: subtract multiplicand.

  • 11 : Middle of a string of 1’s: do no arithmetic operation.

  • 01 : End of a string of 1’s: add multiplicand.

  • 2. Shift multiplicand to the left.

Computer Architecture Project


Integer division
Integer Division multiplication process (Final)

0001 1001 quotient (25)

(10) 0000 1010 divided into 1111 1010 dividend (250)

-1010

1011

-1010

10

101

1010

-1010

0 remainder

Computer Architecture Project


Division algorithm 1

Start: Place Dividend in Remainder multiplication process (Final)

1. Subtract the Divisor register from the

Remainder register, and place the result

in the Remainder register.

Division Algorithm 1

Remainder < 0

Remainder³ 0

Test Remainder

2b. Restore the original value by adding the

Divisor register to the Remainder register, &

place the sum in the Remainder register. Also

shift the Quotient register to the left, setting

the new least significant bit to 0.

2a. Shift the

Quotient register

to the left setting

the new rightmost

bit to 1.

3. Shift the Divisor register right 1 bit.

n+1

repetition?

No: < n+1 repetitions

Yes: n+1 repetitions (n = 8 here)

Done

Computer Architecture Project


Division hardware
Division Hardware multiplication process (Final)

Shift Right

Divisor

16 bits

Quotient

Shift Left

16-bit ALU

8 bits

Write

Remainder

Control

16 bits

Computer Architecture Project


Integer division1
Integer Division multiplication process (Final)

  • ALU, Divisor, and Remainder registers: 16 bit;

  • Quotient register: 8 bits;

  • 8 bit divisor starts in left ½ of Divisor reg. and it is shifted right 1 on each step

  • Remainder register initialized with dividend

Computer Architecture Project


Step by step transition in registors during division process1
Step-by-step transition in registors during division process1

For Version 1:

Computer Architecture Project


Start: Place Dividend in Remainder process1

Division Algorithm (Final)

1. Shift the Remainder register left 1 bit

2. Subtract the Divisor register from the

Remainder register, and place the result

in the Remainder register.

Remainder³ 0

Test Remainder

Remainder < 0

3b. Restore the original value by adding the

Divisor register to the left half of Remainder register, &

place the sum in the left half of Remainder register. Also

shift the Remainder register to the left, setting

the new rightmost bit to 0.

3a. Shift the

Remainder register

to the left setting

the new rightmost

bit to 1.

n

repetition?

No: < n repetitions

Yes: n repetitions (n = 8 here)

Done. Shift left half of Remainder right 1 bit

Computer Architecture Project


Division Hardware (Final) process1

Divisor

8 bits

8-bit ALU

Shift Right

Write

Remainder

Control Test

16 bits

Shift Left

Computer Architecture Project


Step by step transition in registers during division process final
Step-by-step transition in registers during division process (Final)

For Final Version:

Computer Architecture Project


Mult div hardware
Mult/Div Hardware (Final)

Divisor/multiplicand

8 bits

alu_control

Carry-out of adder

8-bit ALU

Shift_left, shift_right

Write

Top half

Control

16 bits

Result/lsb

msb

Computer Architecture Project


"THANK YOU!" (Final)


ad