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Part III. Logic Emulation. What is a Logic Emulation System?. 1. A programmable hardware built with programmable logic (FPGA) and programmable interconnect devices (PID). 2. A software which automatically programs the hardware according to the circuit under design

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Part iii l.jpg

Part III

Logic Emulation


What is a logic emulation system l.jpg
What is a Logic Emulation System?

1. A programmable hardware built with programmable logic (FPGA) and programmable interconnect devices (PID).

2. A software which automatically programs the hardware according to the circuit under design

3. Control HW/SW to support operation of the emulated design as a hardware component operating in real time.


Typical logic emulation environment l.jpg

Workstation

Target System

Logic Emulator

In-circuit

Interface

Logic Module

Probe Module

Typical Logic Emulation Environment

Compiler, runtime software

Stimulus generator, logic analyzer


Why we need logic emulation l.jpg
Why we need Logic Emulation?

  • Design verification issues.

  • Real-time operation.

  • System-level testing.

  • Rapid prototyping.


Design verification issues l.jpg
Design Verification Issues

  • Simulation-based verification methods have run out of steam when chip complexity grows.

  • Emulation is a verification technology that grows along with design size.


Real time operation l.jpg
Real-Time Operation

  • Simulation requires test vector development which is costly and difficult.

    • Verification depends on test vector correctness.

  • Certain applications must be verified in real time - human perception: audio and video.

  • Emulation connected to actual hardware can run:

    • real diagnostic code,

    • operating systems, and

    • applications.


System level testing l.jpg
System-Level Testing

  • Often the chip meets its specifications but it fails in the system.

  • We have to verify the system-level interactions between the chip and other components. They are hard to formalize.

  • Internal probing is impossible when the chip is fabbed and placed in a system

  • But it is possible using emulation.


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Rapid Prototyping

  • Once emulated design is debugged it is available for immediate use by software developers for software debugging.

  • Emulated design is available for demo and experiments with architecture on real applications and data.


Programmable hardware includes programmable interconnect l.jpg

Programmable

interconnect

Interface

Logic

element

Logic

element

Memory

element

VLSI

core

Programmable Hardware includes programmable interconnect


Considerations for programmable interconnect l.jpg
Considerations for programmable interconnect

  • The capacity of logic and interconnection depends on package constraints.

  • This forces a hierarchical system.

    Chips => boards => boxes => system

  • The interconnect structure must:

    1. Provide successful connectivity,

    2. Maximize FPGA utilization, and

    3. Minimize delay and skew.

  • Rent’s rule applies to predict the interconnect needs.


Structures of multi fpga systems l.jpg
Structures of Multi-FPGA Systems

  • Topologies: - Mesh - nearest neighboring. - Crossbar - full and partial.

  • Interconnect scheme: - Circuit switched. - Time multiplexed.


Nearest neighbor interconnection l.jpg

FPGA

FPGA

FPGA

FPGA

FPGA

FPGA

FPGA

FPGA

FPGA

Nearest Neighbor Interconnection


Advantages and disadvantages of nearest neighbor interconnection l.jpg
Advantages and Disadvantages of Nearest Neighbor Interconnection

  • Advantages:

    • Uniform: all chips the same.

    • Easy to lay out on PCB.

  • Disadvantages:

    • Routing is easily blocked.

    • The “through pins” limit the logic utilization of FPGAs.

    • Long and unpredictable delays.

    • No natural hierarchical extension.


Nearest neighbor extensions l.jpg

FPGA Interconnection

FPGA

FPGA

FPGA

FPGA

FPGA

FPGA

FPGA

FPGA

Nearest Neighbor Extensions

Connect to non-neighbors

Add more neighbors


Advantages and disadvantages of nearest neighbor extended architectures l.jpg
Advantages and Disadvantages of nearest-neighbor extended architectures

  • Advantages:

    • More choices for router by adding diagonal lines & skip lines.

  • Disadvantages:

    • More complex PCB.

    • More complex routing software.


Partial crossbar interconnect l.jpg

A B C D architectures

A B C D

A B C D

A B C D

Partial Crossbar Interconnect

Logic blocks

Crossbars

C pins

B pins

D pins

A pins

Second-level crossbars


Partial crossbar interconnect17 l.jpg
Partial Crossbar Interconnect architectures

  • Partial crossbar consists of a set of small full crossbars,

    • connected to logic blocks

    • but not to each other.

  • I/O pins of each FPGA are divided into subsets.

    • Each subset is connected by a full crossbar circuit switch.

  • Partial crossbar is a potentially blocking network.


Characteristics of partial crossbar architecture l.jpg
Characteristics of “Partial Crossbar Architecture” architectures

  • Partial crossbar’s size is proportional to the number of FPGA pins.

  • All interconnections go through one/three crossbar chips for a one-level/two-level partial crossbar interconnect –

    • delays are uniform and bounded.


Mixed full and partial crossbar l.jpg

Global architectures

FPIC

Global

FPIC

Local

FPIC

Local

FPIC

Local

FPIC

FPGA

FPGA

FPGA

FPGA

FPGA

FPGA

Mixed Full and Partial Crossbar

External

connections

Partial

crossbar

Full

crossbar


Circuit switched versus time multiplexed interconnect schemes l.jpg
Circuit Switched versus architecturesTime Multiplexed Interconnect Schemes

  • Trade-offs between the operating speed and the hardware cost.

  • Time-multiplexing method:

    • can greatly expand available interconnect.

    • allows lower cost IC package and PCB.

    • makes partitioning easier.

  • BUT

    • System power increases due to frequent signal switching (higher hardware cost).

    • Complex scheduling software.

    • Slow operating speed.


Virtual wires l.jpg
Virtual Wires architectures

FPGA

FPGA

Logical

outputs

Logical

inputs

Physical

wires

FPGA

FPGA

DeMux

Mux

I change space to time


Logic emulation systems and their interconnection schemes l.jpg
Logic Emulation Systems architecturesand their interconnection schemes

  • System with mesh topology - Quickturn’s RPM and Virtual Machine Works (IKOS).

  • System with partial crossbar - Quickturn’s Enterprise, Mars, and System Realizer.

  • System with mixed full and partial crossbar - Aptix Prototyping System.

  • System using time-multiplexed interconnect - Virtual Machine Works (IKOS) , CoBALT and Arkos (Quickturn).


Memory solutions in emulators and future devices systems l.jpg
Memory Solutions in Emulators and future devices/systems architectures

  • Goal: programmable memories with different width/depth/port combinations.

  • FPGA-based memories:

    • inefficient of using logic resources.

    • timing correctness is difficult to be insured.

    • large or highly multi-ported memories must be partitioned across several FPGAs.

  • SRAMs with dedicated or programmable controllers.


Logic emulation design flow l.jpg

HDL synthesis architectures

Pre-configuration

preparation

Synthesis

Partitioning

System mapping

Full-chip

configuration

P & R

Design downloading

In-circuit

emulation

Emulators

Logic Emulation Design Flow


Logic emulation design compiler and its components l.jpg
Logic Emulation Design Compiler architecturesand its components

  • Logic emulation design compiler is a large and complex EDA tool which includes:

    • Front-end design importer.

    • HDL-based synthesizer.

    • Clock and timing analyzer.

    • Partitioner.

    • System-level placer and router.

    • FPGA-based placer and router.


Objectives of logic emulation compiler l.jpg
Objectives of logic emulation compiler architectures

  • Fast compilation time.

  • Fast emulation clock.

  • Timing correctness.

  • Easy (ECO ENGINEERING Change Order).

  • Minimize circuit size.


Design considerations for logic emulators l.jpg
Design Considerations for Logic Emulators architectures

  • HDL synthesis:

    • Trade-off run-time and quality.

    • CLB-based vs. gate-based designs.

  • Clock and timing analysis:

    • Timing correctness, hold-time violation free.

    • Clock skew minimization.

  • Partitioning:

    • Run time. -

    • Timing and area.


Design considerations for logic emulators28 l.jpg
Design Considerations for Logic Emulators architectures

  • System placement and routing:

    • Timing.

    • Completeness of routing.

  • FPGA-based placement and routing:

    • Fast run time.

    • Parallel compilation.

Remember you emulate not the same logic as your design


Hold time violation l.jpg

Q architectures

Q

D

D

CLB

CK

CK

Routing delay

LUT

Hold-Time Violation

Clock distribution problem (Skew)!!!

Hold-time violation occurs

when Routing delay > LUT delay!!!


Timing correctness l.jpg

Q architectures

Q

D

D

CK

CK

LUT

Timing Correctness

Delay insertion

Delay

element

CLB

Routing delay


Timing correctness31 l.jpg
Timing Correctness architectures

Use clock enables for gated clocks

Q

Q

D

D

LUT

CK

CK

CE

CLB

Clock path

Primary clock

Low-skew net


Methodology and components of logic emulator system l.jpg
Methodology architecturesand components of Logic Emulator System

  • Pre-configuration preparation - prepare netlists and control files for configuration.

  • Testbed preparation - prepare emulation-based operation environment.

  • Full-chip configuration - download design to the emulator.

  • In-circuit emulation - test the design.


Pre configuration in emulator system l.jpg
Pre-Configuration in Emulator System architectures

  • Translate the leaf-cell libraries into emulation primitives.

  • Translated libraries must be verified for functional equivalence to original.

  • Modify and redesign some components to attain compatibility with emulation techniques, such as precharge logic circuits.

  • Assemble all the gate-level netlists for the entire design.


Testbed in logic emulator l.jpg
Testbed in Logic Emulator architectures

  • Design and implement the target ICE boardcombining the emulated design with real hardware.

  • Slowdown testbed to emulation speed.

  • Assemble the testbed and emulation equipment.


Full chip configuration in circuit emulation l.jpg
Full-Chip Configuration & In-Circuit Emulation architectures

  • Full-chip configuration:

    • Prepare control files.

    • Partition the design to fit into the emulation system.

    • Download design into the system.

    • Verify that the emulation model faithfully implements the design as specified by RTL.

  • In-circuit emulation


Part iv l.jpg

Part IV architectures

Reconfigurable Computing and Systems


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General-Purpose Computing vs. Custom Computing architectures

  • General-purpose computing - applying applications on a general-purpose computer.

  • Custom computing - applying applications on a custom-made application-specific hardware.

  • Field-programmable devices make this into a reality.


Goals of reconfigurable computing l.jpg
Goals of Reconfigurable Computing architectures

  • Tailor the architecture to the application.

  • Minimize or eliminate instruction interpretation.

  • Exploit fine grained parallelism.

  • Map software to hardware.


Applications of reconfigurable computing l.jpg
Applications of reconfigurable computing architectures

  • Database search and analysis.

  • Image processing and machine vision.

  • Data compression.

  • Signal processing.

  • Neural networks.

  • Biology computing.

  • Medical computing.

  • Design Automation (PSU)

  • Many more.


Multi mode systems map various applications to a reconfigurable system l.jpg
Multi-Mode Systems architecturesmap various applications to a reconfigurable system

ROM

Reconfigurable

system

Application 1

Application 2

  • Different configurations for read & write

  • operations of a tape driver (Honeywell).

  • Different configurations for different

  • printer controllers (Tektronix).


Run time reconfiguration in military image recognition system l.jpg

Truck? architectures

Run-Time Reconfiguration in military image recognition system

Jeep?

Image data

I/O

?

Tank?

  • Break single computation into multiple pieces.

  • Page in components as needed (virtual hardware),

  • ex., automatic target recognition.


Custom computing l.jpg
Custom Computing architectures

  • Application-specific systems.

  • Numerous applications for similar reconfigurable systems.

  • Offers hardware performance, flexibility to handle numerous algorithms.

  • Multi-FPGA systems can be viewed as hardware supercomputers.

Tell about DEC Perle


Reconfigurable co processors l.jpg

Program 1 architectures

Inst1

Processor

Coprocessor

Reconfigurable Co-processors

Program 2

Inst2

- Provide custom instructions

on a per-application basis.


Types of reprogrammable systems l.jpg

Standalone architectures

PU

Coprocessor

CPU

I/O

interface

Memory

caches

Types of Reprogrammable Systems

Three ways to attach custom computing units

Attached

processing

unit

PU = processing Unit


Types of reprogrammable systems45 l.jpg
Types of Reprogrammable Systems architectures

  • Attached and standalone processing units are reprogrammable systems on computer add-on cards and separate reprogrammable cabinets.

    • Considerations: large communication overhead may over-shadow the speed gain.

  • Application-specific coprocessors can achieve significant improvement over a wide range of applications.


Types of reprogrammable systems46 l.jpg
Types of Reprogrammable Systems architectures

  • Integrate the reprogrammable logic into the processor itself.

    • A reprogrammable functional unit can be configured on a per-algorithm basis.

    • Providing some special-purpose instructions tailored to the needs of a given application.


Architectures of multi fpga reconfigurable systems l.jpg
Architectures of Multi-FPGA (Reconfigurable) Systems architectures

  • The most commonly used topologies:

    • Mesh: 1D (linear array), 2D, and 3D.

    • Crossbar: full, partial, mixed, and hierarchical.

    • Hybrid between mesh and crossbar.

    • Application-specific architecture.


Hybrid topology of a reconfigurable system l.jpg

Ext. Interface architectures

Ext. Interface

FPGA

FPGA

FPGA

FPGA

FPGA

RAM

RAM

RAM

RAM

16 FPGAs

Hybrid Topology of a reconfigurable system

Splash 2: augments a linear array of FPGAs with

a crossbar switch.

Goal: Supporting systolic circuits.


Hybrid topology l.jpg

FPGA architectures

FPGA

FPGA

FPGA

RAM

RAM

RAM

Hybrid Topology

Host

interface

Anyboard: A linear array of FPGAs augmented

by global buses.


Hybrid topology50 l.jpg
Hybrid Topology architectures

RAM

Host

interface

RAM

4 X 4 mesh

of FPGAs

RAM

RAM

DECPeRLe-1: a 4 X 4 mesh of FPGAs augmented

with shred global buses.


Application specific topology of marc 1 one subsystem l.jpg

FPGA architectures

FPGA

FPGA

FPGA

FPGA

FPGA

FPGA

FPGA

FPGA

Memory

FPU

Application-Specific Topology of MARC-1, one subsystem

Connections to other FPGAs

4

5

3

1

2

1

3

4

5

2

1

3

4

2

5

1

The Marc-1: subsystem 1.


Application specific topology of marc 1 cont l.jpg

Subsystem1 architectures

Subsystem1

Application-Specific Topology of Marc-1, cont.

  • Application in circuit simulation where the program to be executed can be optimized on a

  • per-run basis.

    • This is done for values constant within that run,

    • but which may vary from dataset to dataset.

1

The Marc-1

2

3

4

5


Application specific topology l.jpg

RAM architectures

RAM

RAM

FPGA

FPGA

FPGA

FPGA

FPGA

FPGA

RAM

RAM

RAM

Application-Specific Topology

RAM

FPGA

FPGA

FPGA

RAM

RAM

The RM-nc system: neural network.


Architecture for computer prototyping l.jpg
Architecture for Computer Prototyping architectures

VME bus

Cache memory

FPGA

FPGA

FPGA

FPGA

Register file

FPGA

FPGA

FPGA

ALU

FPU

The Mushroom processor

prototyping system.


Expandable topologies l.jpg
Expandable Topologies architectures

  • Hierarchical crossbar topology: can be expanded by adding extra level. - Quickturn systems.

  • Expandable mesh topology: can be expanded by connecting individual boards to form a large mesh.

    • The Virtual Wires Emulation System (IKOS).


Topology for adapting other components l.jpg
Topology for Adapting architecturesOther Components

  • Many multi-FPGA systems include non-FPGA resources to provide more general purpose solutions.

  • The MORRPH system - sockets next to FPGAs which allow to add arbitrary devices to the array.

  • The G800 board - contains two FPGAs and four sockets.


Topology for adapting other components57 l.jpg
Topology for Adapting Other Components architectures

  • The COBRA system

    • Contains:

      • based modules (expanding to 2D mesh),

      • RAM modules,

      • I/O modules,

      • and bus modules.

  • The Springbok system

    • a pre-made daughter board which is able to contain an arbitrary device (on the top) and an FPGA (on the bottom).

    • Daughter boards are mounted on a baseplate.


Topology for adapting other components58 l.jpg
Topology for Adapting Other Components architectures

  • The Quickturn systems - external component adapters.

  • The Aptix FPCB - a reprogrammable PCB.


Design methodology for general purpose configurable systems l.jpg

Applications architectures

Reprogrammable

system

Host

computer

Design Methodology for general-purpose configurable systems

Mapping


Typical software methodology for general purpose configurable systems l.jpg

Code architectures

generation

Application

spec.

System-level

synthesis

Analysis

Hardware

spec.

Software

spec.

Hardware

synthesis

Object code

Typical Software Methodology for general-purpose configurable systems


Typical software methodology for general purpose configurable systems61 l.jpg

Hardware spec. architectures

Synthesis

Bit-stream files

Partitioning & placement

Pin assignment & routing

FPGA P & R

Typical Software Methodology for general-purpose configurable systems


Considerations for such complex software systems l.jpg
Considerations for such complex software systems architectures

  • Architectural-specific design tasks.

  • Design automation process.

  • The mapping time dominates the setup time for operating the system.

  • Run-time reconfigurability.


Design specification and languages for reconfigurable software systems l.jpg
Design Specification and Languages for reconfigurable software systems

  • Standard software programming languages,

    • e.g., C, C++, FORTRAN, and assembly language, vs. HDLs.

  • Standard software programming languages - a sequential execution model.

  • HDLs - a parallel execution model.

  • Who will use it and which one is more suitable for system description???


Compilation issues l.jpg
Compilation Issues software systems

  • Translate code from software languages into hardware without losing the inherent concurrency of hardware.

  • Compiler techniques for parallelizing code.

  • Straight-line code, control flow, and loops.

  • Transmogrifier C compiler.


System level and high level synthesis l.jpg
System-level and High-level Synthesis software systems

  • System-level design evaluation and analysis.

  • Design estimation.

  • Hardware-software partitioning.

  • Interface synthesis.

  • RTL synthesis.

  • Logic synthesis and technology mapping.


Partitioning and placement l.jpg
Partitioning and Placement software systems

  • Topology-aware partitioning methods.

  • Partitioning onto a multi-FPGA system is equivalent to a placement problem.

  • Logic utilization and timing.


Pin assignment and routing l.jpg
Pin Assignment and Routing software systems

  • Pin-assignment - the process of determining which I/O pins to be used for each inter-FPGA signal.

  • Pin-assignment for a pre-fabricated multi-FPGA system is equivalent to the global routing problem.

  • Pin-assignment will greatly affect the quality of FPGA’s logic utilization and routability.


Run time reconfigurability l.jpg
Run-Time Reconfigurability software systems

This is a new issue in system design: how much of the processor is virtual, when to reconfigure?

  • Virtual hardware <=> virtual memory. What are their relations? Artificial Intelligence, robotics. Vision.

  • Hardware on demand.

  • What is the Initial Un-configured structure?What are the reconfiguring methods.

  • Software supporting time-varying mapping.

  • Many open problems need to be solved in the forth coming years.


Applications splash 2 l.jpg
Applications: software systemsSplash 2

  • Stream oriented systolic and SIMD applications.

  • Scalable linear array of 16 to 256 processing elements (1 XC4010 with 1/2 Mbyte).

  • VHDL based.

  • Sequence comparison - 2300M:0.75M cell updates/sec (Splash 2:Sparc 10).

  • Edge detection - 10M:242K pixels/sec (Splash 2:Sparc 10).


Applications pam dec l.jpg
Applications: PAM (DEC) software systems

  • Programmable Active Memory (PAM).

  • C++ based and mesh arrays of XC3090 (DECPeRLe-1).

  • Applications:

    • Multiple precision arithmetic.

    • RSA encryption.

    • Video compression (JPEG, MPEG, DCT). -

    • High energy physics.

    • Telecommunications.


Sources of some slides l.jpg

Sources of some slides software systems

Peter Alfke

Xilinx, Inc

[email protected]


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