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San Jose State University Electrical Engineering. EE-166 4 Bit Serial to Parallel Converter Prof. David Parent, PhD Members: Quang Ly Derek Kwong Hector Vidal. San Jose State University Electrical Engineering. Specifications: Clock f = 25 MHz, duty cycle = 50%

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san jose state university electrical engineering
San Jose State UniversityElectrical Engineering

EE-166

4 Bit Serial to Parallel Converter

Prof. David Parent, PhD

Members: Quang Ly

Derek Kwong

Hector Vidal

san jose state university electrical engineering2
San Jose State UniversityElectrical Engineering

Specifications:

  • Clock f = 25 MHz, duty cycle = 50%
  • Conversion every 4 clock cycles
  • Output Cload = 10 pF
  • Power < 500 mW
san jose state university electrical engineering counter schematic
San Jose State University Electrical EngineeringCounter Schematic:
san jose state university electrical engineering serial to parallel schematic
San Jose State University Electrical EngineeringSerial to Parallel Schematic:
san jose state university electrical engineering output buffer schematic
San Jose State University Electrical EngineeringOutput Buffer Schematic:
san jose state university electrical engineering 4bit serial to parallel test bench schematic
San Jose State University Electrical Engineering4bit Serial to Parallel Test Bench Schematic:
san jose state university electrical engineering simulation waveforms
San Jose State University Electrical EngineeringSimulation waveforms:
san jose state university electrical engineering simulation waveforms10
San Jose State University Electrical EngineeringSimulation waveforms:
san jose state university electrical engineering simulation waveforms reset
San Jose State University Electrical EngineeringSimulation waveforms (Reset):
san jose state university electrical engineering12
San Jose State University Electrical Engineering

Super Buffer Design:

  • Stage 1: Wp=250.4 mm, Wn= 90 mm
  • Stage 2: Wp= 89.2 mm, Wn= 32 mm
  • Stage 3: Wp= 32 mm, Wn= 11.6 mm
  • Stage 4: Wp= 11.6 mm, Wn= 4 mm
  • a= 2.88
san jose state university electrical engineering20
San Jose State UniversityElectrical Engineering

Test results:

  • Rise time (tr) = 3.9 ns
  • Fall time (tf) = 4.05 ns
  • Total area = 22.5 mil2
  • Power < 350 mW
  • Peak current = 16.6 mA
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