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VHDL Project III: Two’s Complement Array MultiplierPowerPoint Presentation

VHDL Project III: Two’s Complement Array Multiplier

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VHDL Project III: Two’s Complement Array Multiplier

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VHDL Project III:Two’s ComplementArray Multiplier

Slides Available at: www.pages.drexel.edu/~mjm46

Matthew Murach

- Design a two’s complement device this is related to homework two and will be collected.
- Discuss the implementation of this device with your array multiplier.
- Discuss possible review sessions for next Wednesday’s midterm.

- Two’s complement operation is performed in the following manner.
0101 (5) 1010 + 1 1011(-5)

0111 (7) 1000 + 1 1001(-7)

- Likewise the reverse is also true
1011 (-5) 0100 + 1 0101 (5)

1001 (-7) 0110 + 1 0111 (7)

- Note that two’s complement uses the following procedure:
1.) Invert the bits

2.) Add one to the result

- There exists another algorithm that computes the two’s complement.

- In Booth’s algorithm, we locate the first 1 starting from the least significant bit (LSB)
- Then we invert the rest.
0111 (7) 1001 (-7)

0100 (4) 1100 (-4)

0100 (4) 1011 + 1 1100 (-4)

- Your two’s complement design should operate with any size vector. That is to say that you must have a generic for the size of the vector.
- Your device should have the following signals control logic, an input vector, and an output vector. Note that you do not have to make your two’s complement synchronous.