1 / 29

An Implementation of JTAG To Avoid Timing Violations and Other Practical In-compliance Improvements

Purpose. To provide an implementation of IEEE 1149.1 that eliminates timing violations without the need for iterations in layoutIn addition show how this implementation can allow scan to be easily inserted for high-coverage manufacturing test. Outline. The timing issues and difficulties as a result of implementing JTAG from the IEEE 1149.1 specificationAn alternate JTAG implementationAdvantages and disadvantages of the alternate implementationExperimental results.

Jims
Download Presentation

An Implementation of JTAG To Avoid Timing Violations and Other Practical In-compliance Improvements

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

    1. An Implementation of JTAG To Avoid Timing Violations and Other Practical In-compliance Improvements 2002 International Test Conference Session 27.1

    2. Purpose To provide an implementation of IEEE 1149.1 that eliminates timing violations without the need for iterations in layout In addition show how this implementation can allow scan to be easily inserted for high-coverage manufacturing test

    3. Outline The timing issues and difficulties as a result of implementing JTAG from the IEEE 1149.1 specification An alternate JTAG implementation Advantages and disadvantages of the alternate implementation Experimental results

    4. The Issues The IEEE 1149.1 specification gives an example implementation using high fan-out gated clocks The gated clocks can have considerable skew due to the distance to the boundary-scan cells around the perimeter of the chip Gated clocks are generally not considered EDA tool friendly Gated clocks and associated logic are difficult to perform manufacture test

    5. The Suggested Implementation Change all the JTAG gated clocks to enables Register all the outputs of the TAP controller Route all boundary-scan control, clocks, and resets the opposite direction of TDI to TDO Add logic to disable the synchronous TAP generated reset

    6. The IEEE 1149.1 Gated Clocks Gated clocks that follow the positive edge of TCK Clock-DR Clock-IR Gated clocks that follow the negative edge of TCK Update-DR Update-IR

    7. Change gated clocks to enables TAP Controller – source of gated clocks Instruction registers – uses gated clocks Clock-IR Update-IR Data registers – uses gates clocks Clock-DR Update-DR

    8. TAP Controller Modifications for Clock-DR

    9. Clock Data Register

    10. TAP Controller Modifications for Clock-IR

    11. Clock Instruction Register

    12. TAP Controller Modifications for Update-DR

    13. Update Data Register

    14. TAP Controller Modifications for Update-IR

    15. Update Instruction Register

    16. Route all boundary-scan control, clocks, and resets the opposite direction of TDI to TDO Assumes that TDI to TDO boundary-scan follow the pads in order around the perimeter of the chip Buffer signals ~20 boundary-scan cells Allows the physical layout of the chip to add desired timing skew to ensure timing is met Timing is met without using layout tool resources

    18. Timing Observations All JTAG clocks, enables, and resets Are buffered with the same architecture Travel the same physical path The skew generated as the clocks, enables, and resets travel around the perimeter Can change considerably between each boundary-scan register Will remain the same relative to each other at each boundary-scan register

    19. Timing Observations (cont) Since the enables are registered on the opposite edge of the data register clock, the enables have a ˝ clock period window Since the data goes in the opposite direction of the control signals, register hold time is met Conclude: Timing is meet by implementation

    20. Timing Diagram

    21. Scan Insertion DFT logic needed to disable synchronous generated TAP reset Scan shift order is the same as the boundary-scan data order (follow TDI to TDO) Scan shift timing is met for the same reason that the JTAG data timing is met

    22. TAP Controller Modifications Synchronous Reset

    23. Findings Implemented into a tool: Astek’s ABC Implemented on several ASICs and different silicon technologies Implementation has not caused any IEEE 1149.1 compliance issues with board testers Timing can be meet by implementation instead of by layout resources Scan can be easily inserted into the JTAG logic with high fault coverage

    24. Silicon Example Results

    25. Silicon Example Results

    26. IEEE 1149.1 Compliance IEEE 1149.1 example and proposed implementation shown equivalent All the IEEE 1149.1 rules are followed in proposed implementation Proposed changes implemented in several ASICs and in different silicon technologies

    27. Advantages Design is EDA tool friendly because the gated clocks were removed Timing is met by implementation Scan is easily inserted with high fault coverage

    28. Disadvantages Higher JTAG gate count (may not be true for high pad count designs) Routing of additional signals Slower clock period required for boundary-scan cell shifting due to daisy-chaining

    29. Conclusion IEEE 1149.1 can be implemented using minimal layout resources trying to meet timing IEEE 1149.1 can be implemented and scan inserted with high fault coverage Let the designer’s design: JTAG insertion does not have to be a hindrance

More Related