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A Study of Delay and Power Consumption of Adders Built with Different Logic Styles

A Study of Delay and Power Consumption of Adders Built with Different Logic Styles. Presented By Xiaoyong Li. Objectives. Implementing 1-bit full adder module with different logic styles, such as static CMOS, TG-CMOS, Differential Cascade Voltage Switch Logic(DCVSL), and Domino logic.

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A Study of Delay and Power Consumption of Adders Built with Different Logic Styles

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  1. A Study of Delay and Power Consumption of Adders Built with Different Logic Styles Presented By Xiaoyong Li ECE8053 Computer Arithmetics

  2. Objectives • Implementing 1-bit full adder module with different logic styles, such as static CMOS, TG-CMOS, Differential Cascade Voltage Switch Logic(DCVSL), and Domino logic. • Measuring the delay and power consumption of the 32-bit ripple-carry adders. • Measuring the delay and power consumption of the 32-bit carry-lookahead adders. • Discussing the simulation results. ECE8053 Computer Arithmetics

  3. 1-bit Full Adder • The Logics of the Sum and Carry-out s = x  y  C in Cout = xy + x  cin + y  cin x, y : two 1-bit operands cin : carry-in s: sum cout : carry-out ECE8053 Computer Arithmetics

  4. X Y S Cin Cout 1-bit Full Adder (Static CMOS) ECE8053 Computer Arithmetics

  5. X Y S Cin Cout 1-bit Full Adder(TG-CMOS) ECE8053 Computer Arithmetics

  6. A B A_ XOR A_ B_ A 2-input XOR Gate(TG-CMOS) ECE8053 Computer Arithmetics

  7. Sum’ Sum A A’ A B B’ B Cin Cin’ The Sum Logic of 1-bit Full Adder(DCVSL) from Dr. Reese’s ece8273 lecture notes ECE8053 Computer Arithmetics

  8. Cout’ Cout A A’ B B’ B Cin Cin’ The Carryout Logic of 1-bit Full Adder(DCVSL) from Dr. Reese’s ece8273 lecture notes ECE8053 Computer Arithmetics

  9. X Y S Cin Cout 1-bit Full Adder (Domino) ECE8053 Computer Arithmetics

  10. CLK A B CLK 2-input Domino OR Gate ECE8053 Computer Arithmetics

  11. Transistor Counts of 1-bit Full Adders Table 1. The Transistor Counts of 1-bit Full Adders ECE8053 Computer Arithmetics

  12. Y31 X31 Y30 X30 Y1 X1 Y0 X0 Cout Cin FA FA FA FA S31 S30 S1 S0 32-bit Ripple-carry Adder ECE8053 Computer Arithmetics

  13. 32-bit Carry Lookahead Adder 16-bit carry lookahead adder 16-bit carry lookahead adder C0 C16 P12 G12 P02 G02 2-bit carry lookahead generator P23 G23 ECE8053 Computer Arithmetics

  14. 16-bit Carry Lookahead Adder Module From Koren Text (Chapter 5) ECE8053 Computer Arithmetics

  15. Circuit Structure Used for Simulations X Sum Y 32-bit adder Cout Cin CLK ECE8053 Computer Arithmetics

  16. Spectre Simulation Results Table 2. Power Consumption and Delay of 32-bit Ripple-carry Adders (50MHz ) ECE8053 Computer Arithmetics

  17. Spectre Simulation Results Table 3. Power Consumption and Delay of 32-bit Carry Lookahead Adders (50MHz ) ECE8053 Computer Arithmetics

  18. Spectre Simulation Results Table 4. The Delay of 32-bit Carry Lookahead Adders for Different Input Switching Frequencies unit (ns) ECE8053 Computer Arithmetics

  19. Discussions and Conclusions • For any of the logic style, the delay of 32-bit carry lookahead adder is much shorter than that of 32-bit ripple-carry adder. • The rankings of the delay and power consumption are not necessarily related to the transistor counts. • TG-CMOS implementation has the longest delay since its 1-bit full adder module cannot provide enough driving capability. The switching activities inside the adder take more time to accomplish. • The delay of the domino logic implementation is the shortest due to its single transistor pull up network(less drain/source, parasitic capacitance at the output node). ECE8053 Computer Arithmetics

  20. Discussions and Conclusions(Cont.) • The DCVSL implementation has the second longest delay although it has the lowest transistor count. The more complex pull down network contributes this conclusion( more drain/source and parasitic capacitances need to be charge or discharged during the switching procedure). • The 32-bit ripple-carry adder consumes less power than the 32-bit carry lookahead adder for any of the logic style because of the carry lookahead generator circuit. • TG-CMOS implementation has the least power consumption since the switching activity occurs less frequently than the other implementations. ECE8053 Computer Arithmetics

  21. Discussions and Conclusions(Cont.) • The domino logic consumes more power than the other three logic styles. The large amount of power is consumed during the precharge period. (2.72mW for evaluation period and 4.27mW for precharge period). • For a given logic style, the delay and power consumption are determined by the input pattern. • For any of the logic style, the 1-bit full adder module can be optimized for either speed or power consumption. • The product of the delay and power consumption is the smallest for the static logic style. The domino logic is the best choice when the faster circuit is required. ECE8053 Computer Arithmetics

  22. References • Ahmed M. Shams, Tarek K. Darwish, and Magdy A. Bayoumi, “ Performance Analysis of Low-Power 1-bit CMOS Full Adder Cells”, IEEE Trans. on Very Large Scale Integration Systems, Vol.10, No.1, pp20-29, February 2002. • Jan. M. Rabaey, ”Digital Integrated Circuits –A Design Perspective ”, Prentice-Hall Inc., 1996. ECE8053 Computer Arithmetics

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