Topic 4: Digital Circuits. (Integrated Circuits Technology). What is on the agenda?. Introduction Basic Operational Characteristics and Parameters of Integrated Circuits CMOS Technology Bipolar Technology Some Practical considerations. 1. Introduction.
Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.
(Integrated Circuits Technology)
Figures 2 and 3 show the CMOS and TTL logic Levels respectively.
Figure 3: Input and output Logic levels for TTL
Figures 2 and 3 show clearly that these two technology don’t support all the ranges of voltages. If and input falls into the unallowed region the behavior of the circuit is unpredicatble, therefore its output doesn’t represent a valuable information
i(t)
VDD
Noise Margin High
Noise Margin Low
NML = VILmax  VOLmax
VDD
VDD
VOHmin
"1"
VIHmin
Undefined
Region
VILmax
VOLmax
"0"
Gnd
Gnd
Gate Input
Gate Output
V(y)
VOH = ! (VOL)
VOL = ! (VOH)
2.4 Static Gate Behavior1 VOH and 0 VOL
! = complement
V(y)
V(y)=V(x)
Switching Threshold
VM
2.5 DC Operation Voltage Transfer Characteristics (VTC)V(y)
f
VOH = f (VIL)
VOL = f (VIH)
VIL
VIH
V(x)
"1"
VIH
Undefined
Region
VIL
VOL
"0"
2.6. Mapping Logic Levels to the Voltage DomainV(y)
Slope = 1
VOH
Slope = 1
VOL
VIL
VIH
V(x)
Fanout – number of load gates connected to the output of the driving gate
N
M
2.8 FanIn and FanOutVout
Ri =
Ro = 0
Fanout =
NMH = NML = VDD/2
Vin
tp = (tpHL + tpLH)/2
50%
tpHL
tpLH
90%
signal slopes
50%
10%
tf
tr
Delay DefinitionsVin
Vout
Vin
input
waveform
t
Vout
output
waveform
t
vout (t) = (1 – e–t/)V
where = RC
R
vout
C
Time to reach 50% point is
t = ln(2) = 0.69
vin
Time to reach 90% point is
t = ln(9) = 2.2
Ppeak = Vddipeak
p(t) = v(t)i(t) = Vddi(t) Pavg= 1/T p(t) dt = Vdd/T idd(t) dt
Source
Drain
Substrate (Body)
(a) NMOS transistor
V
G
V
V
S
D
(b) Simplified symbol for an NMOS transistor
NMOS transistor
Drain
Source
V
DD
Substrate (Body)
(a) PMOS transistor
V
G
V
V
S
D
(b) Simplified symbol for an PMOS transistor
PMOS transistor
DD
R
R
+
5 V
V
V

f
f
V
V
x
x
(a) Circuit diagram
(b) Simplified circuit diagram
x
f
x
f
(c) Graphical symbols
A NOT gate built using NMOS technology
DD
V
f
V
x
1
x
x
f
1
2
0
0
1
V
x
0
1
1
2
1
0
1
1
1
0
(a) Circuit
(b) Truth table
x
x
1
1
f
f
x
x
2
2
(c) Graphical symbols
NMOS realization of a NAND gate
V
DD
DD
V
f
A
V
x
1
x
x
f
1
2
0
0
0
V
x
2
0
1
0
1
0
0
1
1
1
(b) Truth table
(a) Circuit
x
x
1
1
f
f
x
x
2
2
(c) Graphical symbols
Figure 3.8 NMOS realization of an AND gate