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APPLIED SIGNAL PROCESSING AND IMPLEMENTATION. Introduction to 9 & 10th semester Fall 2005. Outline. Basic ASPI Model (A 3 ) Trends from S8 -> S9 -> S10 Course overview Project work Reading suggestions Formation of  project groups Group Rooms, Schedule, Home Page etc. A 3 Paradigm. 1.

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applied signal processing and implementation

APPLIED SIGNAL PROCESSING AND IMPLEMENTATION

Introduction to 9 & 10th semester

Fall 2005

outline
Outline
  • Basic ASPI Model (A3)
  • Trends from S8 -> S9 -> S10
  • Course overview
  • Project work
  • Reading suggestions
  • Formation of  project groups
  • Group Rooms, Schedule, Home Page etc
a 3 paradigm
A3 Paradigm

1

2

4

5

3

Applications

Algorithms

Architectures

  • Application: Non-Linear Signal Processing etc.
  • Algorithm selection
  • Simulation
  • Architecture selection and modelling
  • Design Space Exploration
  • HW/SW Co-Design
basic aspi model a 3
Basic ASPI Model (A3)

Applications

Algorithms

Architectures

For each application => many candidate algorithms

For each algorithm => many implementation architectures

=> Large no. of solutions => Large Design Space

focus of s8aspi
Focus of S8ASPI

Applications

Algorithms

Architectures

1

2

3

  • Application to Algorithm Transformation
  • Simulation & Implementation Environments
focus of s9 aspi
Focus of S9 ASPI

Applications

Algorithms

Architectures

1

2

4

5

1. App -> Alg: Non-Linear Signal Processsing and others

2. Simulation

4-5. Alg  Arch: HW/SW Codesign and Architecture Exploration

focus of s10 aspi
Focus of S10 ASPI

Applications

Algorithms

Architectures

  • Proving your potential for R&D
  • Closing the loop
9th semester applied signal processing and implementation
9th Semester Applied Signal Processing and Implementation
  • THEME:       
    • Non-linear DSP Methods and Real-Time Architectures
  • PERIOD:      
    • 1 September – 31 January
  • PURPOSE:
    • To enable the students to understand, analyze, and employ state-of-the-art DSP methods and algorithms, for example in the domain of non-linear techniques.
    • To enable the students to apply theories and methods to select, analyze and evaluate heterogeneous DSP-processor architectures given a DSP functionality under the constraint of some cost function.
putting it all together
Putting it all together

Design Methodology

8.sem

9.Sem

Algorithm analysis

SW Platform analysis

HW Platform analysis

SW compilers

HW compilers

Design Space Expoloration

9th semester courses
9th Semester Courses 

EL : ELective Course

project work overview
Project Work Overview

Project Development Model

  • Application domain study
  • Algorithm Development and Simulation
  • Design Space Exploration
  • Implementation
  • Evaluation of results
  • Next step
project work overview12
Project Work Overview

Project Development Model

  • Application domain study
  • Algorithm Development and Simulation
  • Design Space Exploration
  • Implementation
  • Evaluation of results
  • Next step
slide15

Project Work Content

  • 2 conventional processor platforms
  • 2 languages
  • Complex Design Software
  • => Keep projects simple(at first)
  • Generic project example:
    • Design, implement and test a processor/coprocessor architecture, that speeds up the execution of a selected algorithm or eventually a family or a set of algorithms
slide16

Project Work Content

An example can be found in:

Accelerating C Software Applications

Results:

Acceleration (@10K iterations)

FPGA, 50MHz w/o I/O .71 3.03 4.69 16.48 144.71 147X

FPGA, 50MHz with I/O 15.61 15.47 15.32 22.74 149.40 106X

Pentium, 3.6GHz 0.64 2.51 5.32 23.11 199.55 104X

PPC405, 400MHz 24.20 242 484 2418 n/a 1

Iterations 100 1000 2000 10000 100000

Notes:

Figure 5. Test results for a range of maximum iteration values demonstrate substantial speedup of

the algorithm (167X when using two parallel processes) compared to an embedded processor

implementation.

slide17

Project Work Content

  • Specific project examples:
  • Vector Co-processor (next pages)
  • Active Noise Cancellation in Headsets, Per Rubak
  • Any suitable algorithm, that you/we may suggest
    • GSM Vocoder (Ch. 5 in SpecC book)
    • H263 Video Decoder (prev. S10 project)
    • RS codec for DVB-H (prev. S10 project)
    • Digital Camera example (Ch. 7 in Vahid’s book)
    • Video filtering
    • 3GDSP algorithm examples
    • A.s.o.
vector inner product 1
Vector Inner Product (1)
  • c = aTb (a transposed times b)

c is a scalar, a and b are vectors (real valued)

  • Ex. (3 elements) Pseudo code

a = [a1, a2, a3]T acc = 0;

b = [b1, b2, b3]T for i=1:3,

c = a1*b1 + a2*b2 + a3*b3; acc = acc + a[i]*b[i];

end;

c = acc;

Parallelism, Control & Communication

How to combine with NIOS/MicroBlaze

When is it beneficial

etc

vector inner product 2
Vector Inner Product (2)
  • Example algoritms
    • FIR filter
      • a represents the filter coefficients
      • b represents the buffer of the signal to be filtered
      • c represents the filtered signal
    • Matrix multiplication may be described as a set of vector inner products.
  • Several matrix operations may be described as sets of vector operations.
slide20

Project Work Details

Application/Algorithm

Application/Algorithm Analysis

(Partial) design methodology

Implementation

SW + HW

MicroBlaze/NiosII + Co-processor

Implementation(s)

SW (PC/AD/ARM) HW(Xilinx/Altera)

Implementation Analysis

Implementation Analysis

Suggestions for HW/SW partitioning

project work results
Project Work Results

See also slide

lab resources
Lab Resources
  • Available platforms:
  • 2 RC100 boards (“small” Xilinx FPGA),
  • 2 RC203 boards (“medium” Xilinx FPGA),
  • 2 Altera boards (“medium” Altera FPGA),
  • TI and AD DSP boards (model ? quantity ?),
  • 1 Lyrtech Signal-Master board (FPGA+DSP, no support!!!)
  • Available development tools:
  • Celoxica DK3 design tools
  • Xilinx & Altera design tools
reading suggestions articles
Reading suggestions/Articles

Closely Coupled Co-processors for Algorithmic Acceleration

Accelerating C Software Applications

Applications of Reprogrammability in Algorithm Acceleration

Algorithmic C Synthesis Fuels Functional Reuse

Using Hardware Acceleration Units in

Software Defined Radio Modem Functions

Finding the best System Design Flow for a High-Speed JPEG Encoder

From C software to FPGA hardware

reading suggestions books
Reading suggestions/Books
  • SpecC: Specification Language and Design Methodology
  • System: Design: A Practical Guide with SpecCSee also SpecC System
  • Embedded System Design: AUnifiedHardware/Software Introduction
formation of project groups
Formation of  project groups
  • Study project ideas carefully
  • Discuss with teachers
  • Prepare for Sept. 14th. a specific project proposal and a list of participants
  • Present your proposal at the next semester group meetingto be held at ???
aspi group rooms home page etc
ASPI Group Rooms, Home Page etc
  • Group Rooms:
    • 9ASPI 12 studerende i 1 grupperum
    • RUM: A6-108/ 36 m2
  • Home Page:

http://kom.aau.dk/~dsp/aspi05-02/sites/default/

  • Secretary:
    • Dorthe Sparre
    • Fredrik Bajers Vej 12, A5-214
    • Phone: +45 9635 8616
    • E-mail: Dorthe Sparre <[email protected]>
9th semester courses27
9th Semester Courses 
  • ASPI9-2A Hardware/Software Codesign
  • Purposes:
  • Give the students the essential knowledge about problems related to the design of modern digital systems for various applications, in particular mobile applications.
  • Make the students understand how to apply digital electronic components efficiently in such systems.
  • Make the students able to apply a systematic design methodology to arrive at near-optimal implementations, using design tools for evaluating a large number of alternatives (Design Space Exploration, DSE).
9th semester courses28
9th Semester Courses 
  • ASPI9-2B Hardware Platform Analysis, Compilation, and optimization
  • Purposes:
  • To provide the students with: knowledge about one particular state-of-the-art IC technology, and comprehension about its usage in modern integrated system design.
  • To make the students understand and apply methods for synthe-sizing from a functional description to an optimal heterogeneous architecture in terms of physical size, execution time, and power consumption.
  • To provide comprehension on syntax and semantics of a specific modern Hardware Description Language (HDL).
  • To make the students able to apply the above topics in terms of formal methods for structures HW/SW Codesign.
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