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A (partial, biased?) history of the MOSFET from a physicist’s perspective. ( i.e. , A brief history of sand). M. Fischetti October 2, 2009. This talk: Void where prohibited, limitations and restrictions apply.

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Slide1 l.jpg

A (partial, biased?) history of the MOSFET

from a physicist’s perspective

(i.e., A brief history of sand)

M. Fischetti

October 2, 2009


This talk void where prohibited limitations and restrictions apply l.jpg
This talk: Void where prohibited, limitations and restrictions apply

  • Technology (i.e., how do we make them?) vs. electronic operation (i.e., how do they work and how do we make them better?)

    • Too much to cover

    • Talk about what I know

    • Major omissions (that is, a disclaimer*):

      • Doping: Diffusion (theory and technology), ion implantation, high-doping effects

      • Lithography, possibly a “technology enabler”: Optical, contact, phase-shift, X-ray…

      • Metallization: Deposition/growth, DAMASCENE, electromigration

      • Etching: Wet vs. dry, RIE, plasma

      • Film growth: Epitaxy, CVD, PE-CVD, MBE, ALD,…

      • Contacts: Silicides, salicides, FUSI,…

      • Layout issues: Isolation (deep/shallow trenches), cross-talk, latch-up, design rules, DRAM/SRAM design, power,…


History of the mosfet what s that l.jpg
History of the MOSFET? What’s that? restrictions apply

  • Thanks to Jiseok Kim for having put me on the spot….

It’s OK… I wish him good luck in getting his PhD wherever ELSE he may wish to get it….

  • I’m not sure what he meant by “history”… So, let’s start from the beginning….


The main character of our story the mosfet l.jpg
The main character of our story: The MOSFET restrictions apply

  • No other human artifact has been fabricated in larger numbers (except perhaps nails?)

  • “…some consider it one of the most important technological breakthroughs in human history…”(Wikipedia, the source of all human knowledge)


Timeline i l.jpg
Timeline I restrictions apply

Technology Physics/Simulations

1925: Julius Edgar Lilienfeld’s MESFET patent

1935: Oskar Heil’s MOSFET patent

194?: Unpublished Bell Labs MESFET

1947: Ge BJT (Bardeen, Brattain, Shockley, Bell Labs)

1954: Si BJT (Teal, Bell Labs)

1960: MOSFET (Atalla&Khang, Bell Labs)

1961: Integrated circuit (Kilby, TI)

1963: CMOS (Sah&Wanlass, Fairchild)

1964: Commercial CMOS IC (RCA)

1965: DRAM (Fairchild)

1968: Poly-Si gate (Faggin&Klein, Fairchild)

1968: 1-FET DRAM cell (Dennard, IBM)

1971: UV EPROM (Frohman, Intel)

1971: Full CPU in chip, Intel 8008 (Faggin, Intel)

1974: Digital watch

1974: Scaling theory (Gänsslen&Dennard, IBM)

1978: Use of ion implanter

1978: Flotox EEPROM (Perlegos, Intel)

1980: Ion-implanted CMOS IC

1980: Plasma etching

1984: Scaling theory <0.25 μm (Baccarani, U. Bologna)

1986: 0.1 μm Si MOSFET (Sai-Halasz, IBM)

1991: CMOS replaces BJT also at high-end

1993: DGFET scalable to 30 nm (theory, Frank et al.)

2007: Non-SiO2 (HfO2–based) MOSFET (Intel)

1955: Si, Ge conduction band (Herring&Vogt)

Deformation-potential, high-field (Bardeen&Shockley)

1957: BTE in semiconductors – impurities (Luttinger&Kohn),

phonons (Price, Argyles)

1964: Band structure calculations (Hermann)

Monte Carlo for semiconductors (Kurosawa)

1965: Linear-parabolic oxidation model (Deal&Grove)

1966: Observations of 2DEG (Fowler, Fang, Stiles, Stern,..)

1967: Conductance technique (Nicollian&Goetzberger)

1974: DDE device simulator (Cottrell&Buturla)

1975: Quantum Hall Effect predicted (Ando)

1979: Quantum Hall Effect observed (von Klitzing)

1981: Identification of native Nit: Pb-centers (Poindexter)

Full-band MC (Shichijo&Hess)

1982: Fractional QHE observed (Störmer&Tsui, Laughlin)

1988: Full-band MC device simulator (MVF&Laux)

1992: NEGF device simulator (Lake, Klimeck, et al.)


Timeline ii l.jpg
Timeline II restrictions apply

Feature size Main Problems

  • 1975: 20 μm (tOX≈250 nm)

  • 1980: 10 μm (tOX≈150 nm)

  • 1985: 5 μm(tOX≈70 nm)

  • 1990: 1 μm(tOX≈15 nm)

  • 1995: 0.35 μm (tOX≈8 nm)

  • 2000: 0.18 μm (tOX≈3 nm)

  • 2005: 65 nm (tOX≈1.4 nm)

  • 2010: 32 nm (tOX≈1.2 nm?)

SiO2growth and instability: Ions, traps, interface

SiO2 instability during operation: electron trapping, NBTI

Hot electron effects: oxidetrapping, VT shift, breakdown

Scaling: Short-channel effects (SCE), oxide, dopants

….life is good…

Scaling: SCE, insulator

Leakage: Insulator

Power: Alternative devices


Timeline iii l.jpg
Timeline III restrictions apply

Feature size Transport Physics

1975: 20 μm

1980: 10 μm

1985: 5 μm

1990: 1 μm

1995: 0.5 μm

2000: 0.25μm

2005: 63 nm

2010: 32 nm

2015: 16 nm ?

Drift-Diffusion

Hydrodynamic/

Energy transport

Boltzmann

Quantum?


Transistor prehistory l.jpg
Transistor prehistory restrictions apply

1935 Heil’s patent 1947 First BJT 1960 Atalla’s MOSFET

Bardeen, Shockley, Brattain (Bell Labs)


Ic prehistory l.jpg
IC Prehistory restrictions apply

1961 Kilby’s first IC 1962 Fairchild IC 1964 First MOS IC

(RCA)


Moore s law prehistory l.jpg
Moore’s law prehistory restrictions apply

Gordon Moore 1965: Cost vs time Moore’s law 1960-1975


Moore s law l.jpg
Moore’s law restrictions apply

Number of transistors/die & feature size vs time


Microprocessor prehistory l.jpg
Microprocessor prehistory restrictions apply

1965: Federico Faggin 1968: Fairchild 8-bit μP 1971: Intel 8080 μP


Memory prehistory dram and eprom l.jpg
Memory prehistory: DRAM and EPROM restrictions apply

Bob Dennard (1-FET DRAM cell, 1968; 1971 Frohman’s UV-erasable EPROM

scaling theory with Fritz Gänsslen,1974) (written by avalanche injection)


More historical trends l.jpg
More historical trends restrictions apply

J. Armstrong (ca.1989)


Timeline ii once more l.jpg
Timeline II once more restrictions apply

Feature size Main Problems

  • 1975: 20 μm (tOX≈250 nm)

  • 1980: 10 μm (tOX≈150 nm)

  • 1985: 5 μm (tOX≈70 nm)

  • 1990: 1 μm (tOX≈15 nm)

  • 1995: 0.35 μm (tOX≈8 nm)

  • 2000: 0.18 μm (tOX≈3 nm)

  • 2005: 65 nm (tOX≈1.4 nm)

  • 2010: 32 nm (tOX≈1.2 nm?)

SiO2growth and instability: Ions, traps, interface

SiO2 instability during operation: electron trapping, NBTI

Hot electron effects: oxide trapping, VT shift, breakdown

Scaling: Short-channel effects (SCE), oxide, dopants

….life is good…

Scaling: SCE, insulator

Leakage: Insulator

Power: Alternative devices


Sio 2 growth and instability l.jpg
SiO restrictions apply2 growth and instability

  • Ionic contamination (K, Na): Unrecognized source of early problems

  • Fixed traps (oxygen vacancies?), especially near Si-SiO2 interface

  • Growth kinetics: Deal & Grove model: linear (reaction-limited) and parabolic (diffusion-limited) regions; dry and wet oxidation rates

  • Interface-state passivation: Al (with H) Post Metallization Anneal (PMA, Peter Balk):

    • H2O → H+ + OH-

    • Si- + H+→ Si-H

Andrew Grove (left), Bruce Deal (center) and Ed Snow (left)

Ed Snow’s cartoon, ca. 1966

about SiO2 instabilities


Sio 2 growth and instability as grown and during operation l.jpg
SiO restrictions apply2 growth and instability, as-grown and during operation

  • CV-plot instabilities (VFBor VT shifts):

    • Ions (mainly Na+ and K+, contamination in chambers, handling, gases, etc…)

    • Interface states generation (stretch-out, Lai, Feigl, Sandia group, Technion, Siemens,…)

    • Electron and hole traps (DiMaria, Young, Feigl):

      • Neutral: H2O-related (mainly OH-) in wet oxides, radiation induced in processing, σ≈ 10-15 to 10-17cm2

      • Charged-attractive: Ionic contamination, σ≈ 10-13 cm2 , field-dependent

      • Charged-repulsive: Radiation-induced, σ≈ 10-19cm2


Sio 2 instability during operation l.jpg
SiO restrictions apply2 instability during operation

  • Anomalous Positive Charge (APC):

    • Caused by electron injection (Avalanche, Fowler-Nordheim) and also hole injection

    • Related to Hydrogen: Boron deactivation in p-type substrates (Sah)

    • Related to hole back-injection from anode? Dependent on gate-metal workfunction - Au vs. Al vs. Mg (MVF&Weinberg, Chenming Hu)

    • Occurring at Si-SiO2interface even under negative bias: Neutral species such as solitons, H2diffusion…? (Weinberg).

    • Connected to wear-out and breakdown (DiMaria, Stathis)

    • Strongly correlated to interface traps (Pb-centers, Lenahan, Poindexter)

    • Oxygen deficiency (Revesz)? Broken Si-H bonds (Si-D experiment, Lyding&Hess)?

  • Negative Bias Temperature Instability (NBTI): No time to discuss, but big issue in high-κdielectrics


Understanding sio 2 degradation two approaches l.jpg
Understanding SiO restrictions apply2 degradation: Two approaches

MVF and DiMaria, INFOS 1989


Sio 2 growth and instability injection techniques and damage generation l.jpg
SiO restrictions apply2 growth and instability: Injection techniques and damage generation


Sio 2 growth and instability electronic transport in sio 2 l.jpg
SiO restrictions apply2 growth and instability: Electronic transport in SiO2

  • Electrons:

    • Long-standing problems of high-field electron transport in polar insulators (Karel Thornber’s 1970 PhD Thesis with Richard Feynman)

    • LO-phonon scattering run-away connected to dielectric breakdown

    • Experimental observations do not show predicted run-away at 2-3 MV/cm

    • Umklapp scattering with acoustic phononskeeps electron energy under control (MVF, DiMaria, Theis, Kirtley, Brorson, 1985)

  • Holes: Small polaron (self-trapping) transport (Bob Hughes’ 1977 time-of-flight experiments explained by David Emin’s 1975 theory).

MVF et al., PR B (1985)


Hot electron effects in constant voltage scaled mosfets l.jpg
Hot electron effects in constant-voltage-scaled MOSFETs restrictions apply

  • Two problems:

    • Understand origin/spectrum of hot carrier

    • Understand nature/process of damage generation

  • Practical problems:

    • Unnecessary and expensive burn-in

    • Wall Street “big glitch” in 1994

  • Theory:

    • Shockley’s “lucky-electron model” widespread in EE community in the ’80s (publicized by Chenming Hu, UCB): Even the Gods can be wrong at times…

    • Full-band models (Sam Shichijo & Karl Hess, MVF&Laux, then others)

    • Basic physics of electron scattering, injection into SiO2, etc.

    • The mid-1990s “pseudo-full-band” frenzy (Bologna, UNC, Udine, Lille, TU-Vienna, Aachen,..): Gain without pain… didn’t work…


Electron injection into sio 2 l.jpg
Electron injection into SiO restrictions apply2

MVF, Laux, and Crabbé, JAP (1996)


Timeline iii once more l.jpg
Timeline III once more restrictions apply

Feature size Transport Physics

1975: 20 μm

1980: 10 μm

1985: 5 μm

1990: 1 μm

1995: 0.5 μm

2000: 0.23 μm

2005: 63 nm

2010: 32 nm

2015: 16 nm ?

Drift-Diffusion

Hydrodynamic/

Energy transport

Boltzmann

Quantum?


Electron transport in si at 3 ev a big headache l.jpg
Electron transport in Si at 3 eV: A big headache restrictions apply

  • Effective-mass approximation valid only for E ≈ a few kBT

  • Scattering rates at E ≥ {a few kBT} totally unknown

  • Moments of the BTE (DDE, Hydrodynamic) not sufficiently accurate


Electron transport in si at 3 ev ca 1992 a depressing picture l.jpg
Electron transport in Si at 3 eV ca. 1992: A depressing picture…

The state-of-the art circa 1992


A good example of experiments theory feedback l.jpg
A good example of experiments-theory feedback picture…

XPS (McFeely, Cartier, Eklund at the

Brookhaven IBM synchrotron line, 1993)

Carrier separation (DiMaria, 1992)

Cartier et al. APL (1993)


Electron transport in si at 3 ev ca 1994 much better l.jpg
Electron transport in Si at 3 eV ca. 1994: Much better… picture…

The state-of-the art circa 1994

MVF et al., JAP (1996)


Scaling l.jpg

1980 picture…→ 1985 → 1988 → 1991 → 1994 → 1999 → 2003 …

LGATE = 10 μm 5 μm 2.5μm 1.3 μm 0.63 μm 0.25 μm 130 nm ….

1980 → 1985 → 1988 → 1991 → 1994 → 1999 → 2003 …

LGATE = 10 μm 5 μm 2.5μm 1.3 μm 0.63 μm 0.25 μm 130 nm ….

1980 → 1985 → 1988 → 1991 → 1994 → 1999 → 2003 …

LGATE = 10 μm 5 μm 2.5μm 1.3 μm 0.63 μm 0.25 μm 130 nm ….

1980 → 1985 → 1988 → 1991 → 1994 → 1999 → 2003 …

LGATE = 10 μm 5 μm 2.5 μm 1.3 μm 0.63 μm 0.25 μm 130 nm ….

1980 →1985 → 1988 → 1991 → 1994 → 1999 → 2003 …

LGATE = 10 μm 5 μm 2.5μm 1.3 μm 0.63 μm 0.25 μm 130 nm ….

1980→ 1985 → 1988 → 1991 → 1994 → 1999 → 2003 …

LGATE = 10 μm 5 μm 2.5μm 1.3 μm 0.63 μm 0.25 μm 130 nm ….

1980→1985 → 1988→ 1991 → 1994 → 1999 → 2003 …

LGATE = 10 μm 5 μm 2.5 μm 1.3 μm 0.63 μm 0.25 μm 130 nm ….

Scaling

  • Shrink dimensions maintaining aspect-ratio

  • Must shrink electrostatic features as well (depletion regions→ doping level and profiles)

1 μm


Scaling30 l.jpg
Scaling picture…

  • Electrostatic integrity (Well-tempered MOSFET, Antoniadis): SOI, DGFETs, FinFETs, NW-FETs

  • Reduce power, an example: The tunnel FET n (tFET)

  • Reduced leakage: High-κgate-insulators

  • Improve (or, at least, maintain) performance: Alternative channel materials?


Scaling electrostatic integrity soi l.jpg
Scaling – Electrostatic integrity: SOI picture…

22 nm strained-Si nFET: SOI to prevent punch- through, strained Si to improve performance (B. Doris, IBM, 2006)




Multibridge fets process flow l.jpg
Multibridge FETs: Process flow SEM)

Samsung Electronics Ltd. (2005)


Scaling electrostatic integrity finfets l.jpg
Scaling – Electrostatic integrity: FinFETs SEM)

Freescale Semiconductors



Scaling reduce power the tunnel fet tfet l.jpg
Scaling – Reduce power: The tunnel-FET (tFET) SEM)

  • Stand-by power dissipation approaching “on” power dissipation… Cannot continue like this!

  • 60 mV/dec → ΔVG ≈ 250 mV for Ioff/Ion ≈ 10-4

  • VT+ ΔVG≥ 0.45 V at 300 K (nFETs)

  • Must increase slope (i.e., go below 60 mV/dec) if we want the `Green’ FET (term coined by C. Hu)

  • Problem: Ion too low in all attempts (DARPA to IBM, UCB, Stanford,…) so far

InAs Tunnel-FET: structure

(M. Haines, UMass 2009)

InAs Tunnel-FET: pair generation rate

(M. Haines, UMass 2009)


Scaling reduce leakage l.jpg
Scaling – Reduce leakage SEM)

  • Off-leakage:

    • Accepted value increasing: Ioff/Ion≈ 10-4 for the 32 nm node (used to be 10-6 or lower!)

    • Connected to electrostatic integrity (punch-through, junction leakage, gate leakage)

  • Gate leakage:

    • C = εox/tox, so if toxhas reached its limit (≈ 1nm, too aggressive so far), scaleεox: High-κ insulators such as HfO2, ZrO2, Al2O3, etc.

  • Problem: Low mobility in high-κ MOS systems (scattering with interfacial optical phonons)

  • Metals with different workfunction needed!

Hi-res TEM from

Susanne Stemmer,

UCSB

MVF et al., JAP (2001)



Scaling improve performance l.jpg
Scaling – Improve performance SEM)

  • Taken for granted early on (ca. 1986)

  • Slow realization that early optimism was unjustified

MVF and S. Laux, EDL (1987)


Scaling improve performance41 l.jpg
Scaling – Improve performance SEM)

  • Look for high-velocity, low-effective mass semiconductors… or should we?

  • Problems:

    • High-energy (≈ 0.5 eV ≈ 20 kBT) DOS and rates identical in most fcc semiconductors

    • Low DOS → loss of transconductance

    • Low DOS → smaller density in quasi-ballistic conditions → lower Ion

    • Low DOS → less scattering in source → source starvation


Scaling improve performance dos bottleneck l.jpg
Scaling – Improve performance: DOS bottleneck SEM)

MVF and S. Laux, TED (1991)


Scaling improve performance strained si l.jpg
Scaling – Improve performance: Strained Si SEM)

MVF and S. Laux, JAP (1996)


Scaling improve performance strained si44 l.jpg
Scaling – Improve performance: Strained Si SEM)

IBM 32 nm strained (tensile)

Si nFET on SiGe virtual substrate

Intel 45 nm strained (compressive)

Si pFET with regrown SiGe S/D


Why are sub 40 nm devices getting slower l.jpg
Why are sub-40 nm devices getting slower? SEM)

  • Power dissipation → reduce frequency or fry!

  • Parasitics play a bigger role (Antoniadis, MIT)

  • Higher oxide fields squeeze carriers against interface → increased scattering (Antoniadis, MIT)

  • Intrinsic Coulomb effects!

MVF and S. Laux, JAP (2001)



Sub 32 nm si cmos devices where do we stand l.jpg
Sub-32 nm Si CMOS devices: Where do we stand? interactions

  • 22 nm: Planar (Intel), SOIs (IBM), FinFETs doable but too expensive.

  • 16 nm: Possibly FinFETs, still Si

  • Below 16 nm:

    • Ge pFETs and III-V nFETs (IMEC)? A pipedream…

    • Ge nFETs still lousy, improvements promised at Dec 2009 IEDM, we’ll see

    • III-Vs in the works:

      • MIT (del Alamo): Great HEMTs, but huge S/D-gate gap not easily scalable

      • SRC/UCSB MOSFETs: Wait and see…


The future and post si cmos devices what do we need l.jpg
The future and “post Si CMOS” devices: What do we need? interactions

  • Three terminal devices (Josephson computers taught us something…!)

  • At least some gain (preserving signal over billions of devices, beating kBT)

  • At least a few devices must have high Ion to charge external loads

  • On/off behavior (Landauer’s water faucet analogy)

  • Low power, possibly non-charge-switching (spins, QCA,…). BUT: If we use ≈ kBT to switch, the heat bath will switch for us even if we do not want to…

  • Notable historic failures:

    • Josephson: Excessively strict tolerances (on insulators), complicated 2-terminal logic

    • SETs: No output current (`a slightimpedance matching issue’, as someone kindly put it….)

    • Optical computers: Photons are huge! Clumsy 3-terminal devices

    • Resonant tunneling diodes and multi-state logic: Non off-off switches, impossible to control manufacturing tolerances

  • High hopes:

    • Nanowires: They are just thin and narrow FinFETs

  • Long shots:

    • Spins and QCA: Low power but no gain

    • CNT: No current in single tube, must use many in parallel

    • III-Vs: Battle already lost in 1991 (DOS bottleneck),,, why bother again?






The lunatic fringe exploratory devices53 l.jpg
The lunatic fringe: Exploratory devices logic technology

Carbon NanoTube (CNT) FET

IFF-Jülich, Germany (2004)


Cnt transistors l.jpg
CNT Transistors logic technology

IFF-Jülich, Germany (2004)


Cnt fet inverter l.jpg
CNT FET inverter logic technology

J. Appenzeller, IBM


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