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Chapter 3

Instruction Set Architecture. ISA Includes the information needed to interact with the microprocessor.Does not include information as to how microprocessor is designed or implementedIncludes microprocessor instruction set, which would be the set of all assembly languages instructions.Also includes the complete set of accessible registers..

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Chapter 3

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    1. Chapter 3 Instruction Set Architectures

    2. Instruction Set Architecture ISA Includes the information needed to interact with the microprocessor. Does not include information as to how microprocessor is designed or implemented Includes microprocessor instruction set, which would be the set of all assembly languages instructions. Also includes the complete set of accessible registers.

    3. 3.1 Levels of Programming Languages Programming languages are divided into three categories. High level languages hide the details of the computer and operating system. Are also referred to as platform-independent. Examples include C++, Java, and Fortran

    4. 3.1 Levels of Programming Languages (contd) Assembly language is an example of a lower level language. Each microprocessor has its own assembly language A program written in the assembly language of one microprocessor cannot be run on a different microprocessor

    5. 3.1 Levels of Programming Languages (contd) Backward compatibility used in order to have old programs that ran on a old microprocessor, can run on a newer model. Assembly language can manipulate the data stored in a microprocessor. Assembly language are not platform independent

    6. 3.1 Levels of Programming Languages (contd) Lowest level of languages are machine language. Contains binary values to cause microprocessor to perform operations. Microprocessor understands the machine language, and thus it is in this state that it executes a instruction set. High level language and assembly language are converted to machine language.

    7. 3.1.2 Compiling and Assembling Programs High-level language programs are compiled Assembly languages are assembled.

    8. 3.1.2 Compilers Compiler checks statement in a program is valid. If every instruction is syntactically correct, then the compiler generates a object code. Linker combines object code as an executable file. Executable file copied into memory, and microprocessor then runs the machine code contained in that file

    9. 3.1.2 Compilers (contd) A high-level language statement is usually converted to a sequence of several machine code instructions. Every high-level language statement might have more then one valid conversion of a statement.

    10. 3.1.2 Assemblers Every statement in assembly language however corresponds to one unique machine code instruction. The assembler converts source code to object code, and then the linking, and the loading of procedures occur.

    11. Compiler vs Assembler

    12. 3.2 A closer look at Assembly Language Assembly language is very important part of a instruction set architecture. Assembly instructions can be grouped together based on their functions.

    13. 3.2.1.1 Data Transfer Instructions Related with moving data from one place to another. Not be mistaken as the idea that data is literally moved, instead it is copied from one location to another. This particular type of instruction set does not modify data.

    14. 3.2.1.1 Data Transfer Instructions (contd) Instructions related with this category perform the following transfers: Load data from memory into microprocessor. Store data from the microprocessor into memory. Move data within the microprocessor. Input data to the microprocessor. Output data from the microprocessor.

    15. 3.2.1.2 Data Operation Instructions Data operation instructions modify their data values. They require one or two operands, and then they store the result Arithmetic instructions make up a large part of the data operation instructions. Logic instructions perform basic logical operations on data. Shift instructions shift bits of data values in a register.

    16. 3.2.1.3 Program Control Instructions For Assembly languages, the jump or branch instruction is commonly used to go to another part of the program. An assembly language instruction set may include instructions to call and return from subroutines. Microprocessor can also be designed to accept interrupts, which basically causes a microprocessor to stop its current process, and execute another set of instructions.

    17. 3.2.2 Data Types Numeric data can be represented as integers: Unsigned integers of n-bit values can range from 0 to 2^n-1. Signed n-bit integers can have values between 2^n-1 to 2^n-1-1

    18. 3.2.2 Data Types (contd) Other types include: Float: Microprocessor may have special registers only for floating point data, and its corresponding instruction set. Boolean: Instructions can perform logical operations on these values. Characters: Stored as binary values. Operations include concatenation, replacing characters, or character string manipulation.

    19. 3.2.3 Addressing Modes Microprocessor needs memory address to access data from the memory. Assembly language may use several addressing modes to accomplish this task.

    20. 3.2.3 Addressing Modes (contd) 3.2.3.1 Direct Mode Instruction includes memory access. CPU accesses that location in memory. Example: LDAC 5 Reads the data from memory location 5, and stores the data in the CPUs accumulator.

    21. 3.2.3 Addressing Modes (contd) 3.2.3.2 Indirect Mode Address specified in instruction contains address where the operand resides. Example: LDAC @5 or LDAC (5) Retrieves contents of location 5, uses it to access memory addrss

    22. 3.2.3. Addressing Modes (contd) 3.2.3.3 Register Direct and Register Indirect Modes Does not specify a memory address. Instead specifies a register. Example: LDAC R Where R is a register containing the value 5. The instruction copies the value 5 from register and into the CPUs accumulator.

    23. 3.2.3 Addressing Modes (contd) 3.2.3.4 Immediate Mode The operand specified in this mode is the actual data it self. Example: LDAC #5 Moves the value 5 into the accumulator.

    24. 3.2.3 Addressing Modes (contd) 3.2.3.5 Implicit Mode Does not exactly specify an operand. Instruction implicitly specifies the operand because it always applies to a specific register. Example: CLAC Clears the accumulator, and sets value to zero. No operands needed.

    25. 3.2.3 Addressing Modes (contd) 3.2.3.6 Relative Mode Operand supplied is an offset, not the actual address. Added to the contents of the CPUs program counter register to generate the required address. Example: LDAC $5 is located at memory location 10, and it takes up two blocks of memory. Thus the value retrieved for this instruction will be 12 + 5, and will be stored in the accumulator

    26. 3.2.3 Addressing Modes (contd) 3.2.3.7 Index Mode and Base Address Mode Address supplied by the instruction is added to the contents of an index register. Base address mode is similar except, the index register is replaced by a base address register. Example: LDAC 5(X) where X = 10 Reads data from location (5 + 10) = 15 and stores it in the accumulator.

    27. 3.2.3 Addressing Modes (contd) Summary a) 0: LDAC 5 (instruction gets data from location 5) 5: 10 stores value in CPU 0: LDAC @5 (instruction gets address from location 5) 5: 10 (then gets data from location 10) 10: 20 stores value in CPU c) 0: LDAC R instruction gets address from register R R: 5 stores value in CPU d) 0: LDAC R instruction gets address from register R : 5 then gets data from location 5 5: 10 stores value in CPU e) 0: LDAC # 5 stores value from instruction in CPU f) 0: LDAC (implicit) instruction gets value from stack stack stores value in CPU g) 0: LDAC $5 1: instruction adds address of next instruction (1) to 5: offset (5) to get address (6) 6: 12 stores value in CPU

    28. 3.2.4 Instruction Formats Assembly language in machine language is represented as binary value called instruction code. Binary value for each instruction is in different format. Representation of operation to be performed is called opcode.

    29. 3.2.4 Instruction Formats (contd) Examples ADD = 1010 A = 00 MOVE = 1000 B = 01 LOAD = 0000 C = 10 STORE = 0001 D = 11 PUSH = 0100 POP = 1100

    30. 3.2.4 Instruction Formats Examples (contd) A) ADD A,B,C (A=B+C) 1010 00 01 10 B) MOVE A,B (A = B) 1000 00 01 ADD A,C (A = A + C) 1010 00 10 C) LOAD B (Acc = B) 0000 01 ADD C (Acc = Acc + C) 1010 10 STORE A (A = Acc) 0001 00 D) PUSH B (Stack = B) 0101 PUSH C (Stack = C,B) 0110 ADD (Stack = B + C) 1010 POP A (A = stack) 1100 Fewer bits requires less hardware, but more instructions. Fewer bits allows faster execution.

    31. 3.3 Instruction Set Architecture Design To design a optimal microprocessor, the following questions and issues have to be addressed in order to come up with an optimized instruction set architecture for the CPU: Completeness; does the instruction set have all of the instructions a program needs to perform its required task. Issue of orthogonality, the concept of two instructions not overlapping, and thus not performing the same function. The amount of registers to be added. More registers enables a CPU to run faster, since it can access and store data on registers, instead of the memory, which in turn enables a CPU to run faster. Having too many registers adds unnecessary hardware. Does this processor have to be backward compatible with other microprocessors. What types and sizes of data will the microprocessor deal with? Are interrupts needed? Are conditional instructions needed?

    32. 3.4 Creating a simple Instruction Set Designing a simple microprocessor fit for maybe a microwave will involve integrating the following models: Memory model Register model Instruction set

    33. 3.4.1 Memory Model Microprocessor can access 64 K or 2^16 byes of memory Each byte has 8 bits or 64K x 8 of memory. I/O is treated as memory access, thus requires same instruction to access I/O as it does to access memory

    34. 3.4.2 Registers Three registers in this microprocessor First register is 8-bit accumulator where the result is stored. Also provides one of the operands for instructions requiring two operands. Second register R is a 8-bit register that provides the second operands, and also stores in result so that the accumulator can gain access to it. Third register is a Z register which is 1 bit. It is either 0 or 1. If a result of a instruction is 0 then the register is set to 1 otherwise it is set to 0.

    35. 3.4.3 Instruction Set 16 instructions, 8-bit each:

    36. 3.4.3 Instruction Set (contd) Note: LDAC uses direct addressing mode. MOVR uses the implicit addressing mode. JUMP uses immediate addressing mode.

    37. 3.4.4 Implementation 1 + 2 + + n, or Total = 0 For I = 1 TO N do (Total = Total + I); Break Down: 1: Total = 0, I = 0 2: I = I + 1 3: Total = Total + I 4: If I ? n THEN GOTO 2

    38. 3.4.4 Implementation (contd) CLAC Clear Accumulator STAC total Store value 0 to address total STAC i Store value 0 to address i Loop: LDAC i Load contents of address i into accumulator INAC Add 1 to the accumulator STAC i Store result from accumulator back to address i MVAC Move result from accumulator into Register R LDAC total Load Total into accumulator ADD Add contents of Register R and accumulator and store it in accumulator STAC total Store Total back to address total LDAC n Load n into accumulator SUB Subtract R (R = i) from AC (AC = n) JPNZ Loop If result is not zero then jump back to loop:

    39. 3.4.4 Implementation (contd)

    40. 3.4.5 Analysis of Instruction Set, and Implementation Cannot have value greater then 255, therefore n has to be less then or equal to 22 Is it complete? For simple hardware, maybe. Not enough to be implemented in a PC. Fairly orthogonal; however by eliminating OR and implementing by AND and NOT, we can reduce the amount of hardware used. Not enough registers.

    41. 3.5 8085 Microprocessor Instruction Set Archtecture Processor has practical applications. Examples include the Sojourner robot. Contains several registers including the accumulator register, A. Other registers include B,C,D,E,H,L. Some are accessed as pairs. Pairs are not arbitrary. B and C, D and E, H and L. SP is a 16 bit stack pointer register pointing to the top of the stack.

    42. 3.5 8085 Microprocessor Instruction Set Archtecture Contains five flags known as flag registers: Sign flag, S indicates sign of a value Zero flag, Z, tells if a arithmetic or logical instruction produced 0 for a result. Parity flag, P, is set to 1 if result contains even number of 1s Carry flag, CY, is set when an arithmetic operation generates a carry out.

    43. 3.5 8085 Microprocessor Instruction Set Archtecture Auxiliary carry flag, generates a carry out from a lower half of a result to a upper half. Example: 0000 1111 + 0000 1000 = 0001 0111 IM register used for enable and disable interrupts, and to check pending interrupts.

    44. 3.5.2 8085 Microprocessor Instruction Set Contains a total of 74 instructions.

    45. 3.5.2 Data movemement instruction for the 80855 microprocessor

    48. 3.5.2 Program control instruction

    49. 3.5.3. A Simple 8085 Program 1: i = n, sum = 0 2: sum = sum + i, i = i - 1 3: IF i ? 0 then GOTO 2 4: total = sum

    50. 3.5.3 A Simple 8085 Program (contd) LDA n MOV B, A XRA A Loop: ADD B DCR B JNZ Loop STA total

    51. 3.5.3 Execution trace

    52. 3.5.4 Analyzing the 8085 ISA Instruction set more complete then the simple CPU, however not sufficient enough for a PC. Able to use subroutines, and interrupts It is fairly orthogonal. Has sufficient number of registers

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